CCD多晶硅层间绝缘介质对器件可靠性的影响

采用扫描电子显微镜和电学分析技术研究了电荷耦合器件(CCD)多晶硅层间绝缘介质对器件可靠性的影响.研究结果表明,常规热氧化工艺制作的多晶硅介质层,在台阶侧壁存在薄弱区,多晶硅层间击穿电压仅20 V,器件在可靠性试验后容易因多晶硅层间击穿而失效.采用LPCVD淀积二氧化硅技术消除了多晶硅台阶侧壁氧化层薄弱区,其层间击穿电压大于129 V,明显改善了器件可靠性.     

n~+多晶硅上热生长SiO_2薄膜的电传导和击穿特性

我们用斜坡电流电压(I-Y)测量方法分析了n~+型无定形淀积多晶硅上热生长SiO_2的传导和击穿特性。结果表明,和在体硅上生长的SiO_2相比,在多晶硅上生长的氧化层(多晶氧化层)的绝缘特性要差一些,这可直接归因于由氧化引起的界面粗糙化——这种界面粗糙化导致了氧化层电场的局域增强。例如,我们在测量中发现,167(?)厚多晶氧化层的击穿电场E_(BD)大约为9.5MV/cm,Fowler—Noodheim隧道效应的有效势垒高度φBeff高达2.78eV,这表明,该厚度的多晶氧化层的性质与体SiO_2是接近的。但是,E_(BD)和φBeff都随着多晶氧化层厚度D_(ox)的增大而逐渐减小。当厚度为165(?)时,E_(BD)近似为2.5MV/cm,而φBeff下降到只有0.83eV。随着D_(ox)的增大,我们发现测出的I-V曲线与外加电压极性的关系越来越密切,这是因为多晶硅/硅界面的氧化诱生界面粗糙化程度比氧化层/多晶硅界面严重,由于Fowler-Noodheim电子注入效应,多层晶硅/硅界面的“导电能力”要高于氧化层/多晶硅界面。 某些器件应用领域要求多晶氧化层具有一定的导电能力,能够通过较大的电流密度而不失效。为此,人们开发了一种多晶硅纹理化方法,对于随后形成的薄多晶氧化物,采用这种方法可减小φBeff,增大击穿电流I_(BD),并可消除I-V曲线对外加偏压极性的依赖关系。该工艺     

CCD多晶硅层间复合绝缘介质研究

电荷耦合器件(CCD)多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。将氮化硅和二氧化硅作为CCD多晶硅层间复合绝缘介质,采用扫描电子显微镜(SEM)和电学测试系统研究了多晶硅层间氮化硅和二氧化硅复合绝缘介质对CCD多晶硅栅间距和多晶硅层间击穿电压的影响。研究结果表明,多晶硅层间复合绝缘介质中的氮化硅填充了多晶硅热氧化层的微小空隙,可以明显改善绝缘介质质量。多晶硅层间击穿电压随着氮化硅厚度的增加而增大,但太厚的氮化硅会导致CCD暗电流明显增大。由于复合绝缘介质质量好,可以减小CCD多晶硅的氧化厚度。     

超薄氧化层的电击穿特性

本文在测试分析N 理层—隧道氧化层一多晶硅电容（N OP电容）、P衬底一隧道氧化层一多晶硅电容（POP电容）和EEPROM单元隧道氧化层电容（TOP电容）的I－V特性、I－t特性、V－t特性的基础上,对隧道氧化层的击穿特性进行了理论分析,并提出了提高隧道氧化层可靠性的具体措施。     

多场极板LEDMOS表面电场和导通电阻研究

研究了常规LEDM O S,带有两块多晶硅场极板LEDM O S以及带有两块多晶硅场极板和一块铝场极板的LEDM O S表面电场分布情况,重点研究了多块场极板在不同的外加电压下,三种LEDM O S的表面峰值电场和导通电阻的变化情况。模拟结果和流水实验结果都表明:多块场极板是提高LEDM O S击穿电压的一种有效方法,而且场极板对导通电阻的影响很小。研究结果还表明:由于金属铝引线下面的氧化层很厚,所以铝引线几乎不会影响到LEDM O S的击穿特性。     

多晶硅发射极晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能进行了比较.结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了EB击穿和CB击穿.电流增益依赖于淀积多晶硅前的表面处理条件.     

多晶硅部分剥离技术对抗辐照VDMOS动态特性的影响

在考虑VDMOS器件的抗辐照特性时,为了总剂量辐照加固的需求,需要减薄氧化层的厚度,然而,从VDMOS器件的开关特性考虑,希望栅氧化层厚度略大些。本文论证了在保证抗辐照特性的需求的薄氧化层条件下,采用漂移区多晶硅部分剥离技术以器件动态特性的可行性,研究了该结构对器件开启电压、击穿电压、导通电阻、寄生电容、栅电荷等参数的影响,重点研究了漂移区多晶硅窗口尺寸对于VDMOS动态特性的影响。模拟结果显示,选取合理的多晶硅尺寸,可以降低栅电荷Qg,减小了栅-漏电容Cgd,减小器件的开关损耗、提高器件的动态性能。     

衬底热空穴耦合的薄栅TDDB效应

通过衬底热空穴 (SHH,Substrate Hot Hole)注入技术 ,对 SHH增强的薄 Si O2 层击穿特性进行了研究 .与通常的 F- N应力实验相比 ,SHH导致的薄栅氧化层击穿显示了不同的击穿特性 .其击穿电荷要比 F- N隧穿的击穿电荷大得多 ,栅氧化层的击穿电荷量与注入的空穴流密度和注入时空穴具有的能量以及栅电压有关 .这些新的实验结果表明 F- N应力导致的薄栅氧化层的击穿不仅由注入的空穴数量决定 .提出了一个全新的衬底热空穴耦合的TDDB(Tim e Dependent Dielectric Breakdown)模型     

衬底热空穴耦合的薄栅TDDB效应

通过衬底热空穴(SHH,Substrate Hot Hoel)注入技术,对SHH增强的薄SiO2层击穿特性进行了研究.与通常的F-N应力实验相比,SHH导致的薄栅氧化层击穿显示了不同的击穿特性.其击穿电荷要比F-N隧穿的击穿电荷大得多,栅氧化层的击穿电荷量与注入的空穴流密度和注人时空穴具有的能量以及栅电压有关.这些新的实验结果表明F-N应力导致的薄栅氧化层的击穿不仅由注入的空穴数量决定.提出了一个全新的衬底热空穴耦合的TDDB(Time Dependent Dielectric Breakdown)模型.     

多晶硅有晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能的进行比较。结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了ＥＢ击穿和ＣＢ击穿,电流增益依赖于淀积多晶硅前的表面处理条件。     

Silicon nano-asperities: Morphological evolution and electrical properties of double-polysilicon interlayers

Polysilicon/silicon-dioxide/polysilicon structures (double polysilicon) are grown by deposition of amorphous silicon followed by thermal oxidation and a final polysilicon deposition process. Correlation between the appearance of silicon nano-structures and surface morphology formed during the amorphous silicon deposition stage and the electrical characteristics of the double poly capacitor have been investigated. It is shown that the process parameters have a pronounced effect on the morphological properties of the film surface. Nanometric size asperities form during the amorphous silicon deposition stage. The density and height distribution of these asperities were found to depend on deposition temperature. Thermal oxidation of the amorphous layer resulted in the growth of a top oxide layer and crystallization of the bottom silicon film. This process results in an overall increase of the surface roughness and a pronounced decrease in the height of the nano-asperities. By HF-etching the oxidized film, the surface of the polycrystalline silicon is exposed. Following this etching process, the surface roughness increases, whereas the density and height of the nano-asperities decrease. A correlation between the height of asperities on the bottom amorphous silicon film (as well as roughness of this film) and the breakdown voltage of the double poly was found.     

Polyoxides grown on n+ polysilicon

The polarity asymmetry on the electrical characteristics of the oxides grown on n⁺ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N₂ pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased     

Characterization of polysilicon oxides thermally grown anddeposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q_bd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device Structure

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from the back-gate bias $V_{rm bg}$, resulting in a constant breakdown voltage (BV) and the same electric field and potential distributions in the SOI layer, UBO, and polysilicon under different the back-gate biases for a CBL SOI REduced SURface Field (RESURF) Lateral Double-diffused MOS (LDMOS). $V_{rm bg}$ only impacts the field strength and voltage drop in the lower buried oxide (LBO) layer. Moreover, based on the continuity of electric displacement, the holes enhance the field in the LBO from 80 $hbox{V}/muhbox{m}$ of the conventional SOI to 457 $hbox{V}/muhbox{m}$ at $V_{rm bg} = hbox{0 V}$, leading to a high BV. A 747-V CBL SOI LDMOS is fabricated, and its eliminating back-gate bias effect is verified by measurement. In addition, the CBL SOI structure can alleviate the self-heating effects due to a window in the UBO.      

Improvement of polysilicon oxide characteristics by fluorineincorporation

The effect of fluorine on the polysilicon oxide (polyoxide) characteristics is investigated. It is found that the polyoxide leakage current and breakdown strength are improved as fluorine is incorporated into the oxide film. Experimental results show that the improvement is believed to be due to the oxide stress relaxation rather than the change of the polyoxide/polysilicon interface texture     

Observation of high interface state densities at the silicon/oxide interface for low doped polysilicon/oxide/silicon capacitor structures

In this work, we present new observations noted in the capacitance–voltage behaviour of polysilicon/oxide/silicon capacitor structures. As the active doping concentration reduces in the polysilicon layer, an anomalous capacitance–voltage behaviour is measured which is not related directly to depletion into the polysilicon gate. From examination of the frequency dependence of the capacitance–voltage characteristic, in conjunction with analysis and simulation, the anomalous capacitance–voltage behaviour is explained by the presence of a high density of near-monoenergetic interface states located at the silicon/oxide surface. The density and energy level of the interface states are determined. Furthermore, the work presents a mechanism by which the polysilicon doping level can impact on the properties of the silicon/oxide interface.     

High quality interpoly dielectrics deposited on thenitrided-polysilicon for nonvolatile memory devices

High quality interpoly dielectrics have been fabricated by using NH₃ and N₂O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N₂O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm² ) and electric breakdown field (up to 17 MV/cm)     

Electroactive Centers at the Outer Interface of an Ultrathin Oxide Layer and Their Effect on the Electrical Performance of Single-Crystal Silicon/Noncrystalline Oxide/Polysilicon Structures

Single-crystal silicon/noncrystalline ultrathin oxide multilayer structures were investigated. The oxide was formed by (100)Si thermal oxidation. An undoped polysilicon layer with an aluminum contact was used as a gate. The distribution of ionized electroactive centers (defects) in the ultrathin oxide and the energy spectrum of the centers at the oxide interfaces and near the polysilicon surface were considered. It was found that the centers at the outer interface of the oxide affect the electrical performance of the multilayer structures.     

Investigation of the doping and thickness effects of polysilicon oxide by rapid thermal N2O oxidation

In this paper, polyoxides were grown on n+ doped polysilicon by using rapid thermal N₂O processing. The doping level of the lower polysilicon layer and the polyoxide thickness effect were investigated. Results showed that N₂O oxide grown on medium-doped polysilicon layer exhibited better characteristics than that grown on heavily-doped polysilicon layer. The polyoxide/polysilicon interface of the polyoxide grown on the heavily doped bottom poly-1 layer is smoother than that of the medium doped polyoxide, apparently due to the phosphorus concentration which facilitates SiO₂ viscous flow and prevents oxide thinning and horn formation. However, despite the smoother interface, a large amount of phosphorus via out-diffusion after subsequent oxidation process accumulates at the polysilicon/polyoxide interface and is incorporated into the polyoxide, degrading the oxide quality. Therefore, to obtain better characteristics from N₂O polyoxide grown on a medium-doped polysilicon layer, an appropriate amount of phosphorus and nitrogen should be incorporated. Further, the thicker the oxide, the worse the characteristics, due to the longer oxidation time, which results in a rougher interface, leading to larger charge trapping and smaller Qbd.