一种瞬态增强的无外接电容LDO电路设计

设计了以增强型AB跟随器作为缓冲级的带瞬态增强电路的线性稳压器(LDO)。在保证LDO环路稳定性的同时,将增强型AB跟随器的偏置电流改为动态偏置电流,同时加入瞬态增强电路来改善系统重载到轻载来回跳变时的瞬态性能。仿真结果表明,该稳压器输入电压2.7~5 V,输出电压2.5 V,压差200 m V,电路空载时静态电流18μA,最大负载电流100 m A;在输出电容为100 pF时,负载电流以99×10~(–3)A/μs跳变,输出电压下冲和过冲分别为89 m V和110 m V,均在1.5μs内恢复稳定。     

无输出电容的瞬态增强NMOS LDO

提出了一种用于片内数字驱动的瞬态增强NMOS低压差线性稳压器(LDO)。该LDO采用电容耦合动态偏置和双环路推挽式驱动调整管,极大地提高了电路的瞬态响应速度。基于0.35 μm BCD工艺的仿真结果表明,负载电流在0.1~100 mA之间的跃迁时间为100 ns时,电路的下冲电压为42 mV,过冲电压为66 mV,稳定时间仅为323 ns。该LDO电路的总体静态电流约为50 μA,输出电流最大值为100 mA。     

一种基于电流比较的无基准电压Cap-less LDO

提出了一种基于电流比较的无基准电压型Cap-less LDO。将输出电压转换为电流后与参考电流比较,无需独立的基准电压模块,可降低功耗。在环路中插入了一个带有源反馈补偿网络的误差放大器,可增加环路增益,从而提升精度,在减少片上补偿电容的同时维持宽负载范围内的环路稳定性。该LDO采用65 nm标准CMOS工艺仿真验证,仿真结果显示,当负载电容为100 pF时,静态电流为9.4 μA,片上补偿电容仅需0.25 pF,当输出负载在100 μA和50 mA之间处切换时,恢复时间小于1 μs,带有源反馈LDO的上冲和下冲分别为94 mV和21 mV,和不带有源反馈的LDO相比,上冲和下冲分别减少了28%和79%。     

适用于高频开关芯片的快速瞬态响应LDO设计

设计了一种片外大电容快速瞬态响应低压差线性稳压器。该LDO电路基于跨导线性结构设计,在输出级引入推挽结构,有效地减小过冲的幅值和恢复时间,提高了LDO的瞬态响应速度;利用浮动缓冲器驱动功率管,有效地提高了LDO的电流效率;采用动态零点补偿技术,保证了LDO在全负载范围内的环路稳定性。该LDO电路基于0.35μm BCD工艺设计与仿真验证。结果表明,在1.2 V~3 V输入电压范围,LDO的输出电压为1 V,静态电流约为50μA,可提供0~300 mA的负载。在上升下降沿为500 ns、幅度为300 mA、轻载持续时间为50μs的负载瞬态跳变下,过冲和下冲均小于20 mV。电路满足高频负载跳变的应用需求。     

一种低功耗无片外电容LDO的设计

基于SMIC 0.18 μm CMOS工艺,设计了一款输入电压为1.8 V、输出电压为1.6 V的低功耗无片外电容低压差线性稳压器(LDO),其静态电流仅为5 μA。该电路采用一种新型摆率增强电路,通过检测输出电压的变化实现对功率管的瞬态调节。片内采用密勒补偿使主次极点分离,整个系统在负载范围内具有良好的稳定性。仿真结果显示,该LDO在负载电流以99 mA/1 μs跳变时,输出电压下冲为59 mV,上冲为60 mV,响应时间约为1.7 μs。     

基于高压摆率误差放大器和摆率增强电路的无片外电容LDO

基于0.35μm CMOS工艺设计了一款无片外电容低压差线性稳压器(cap-free LDO),通过误差放大器组成的环路控制稳态误差,通过摆率增强电路构成的环路改善瞬态响应。该LDO输出电压为1.72V,压差80mV,最大输出电流50mA。测试结果显示:负载电流(IL)在0.5μs内瞬变50mA时,俯冲电压和过冲电压均为80mV左右,重回稳态的时间均小于1.5μs。     

基于高摆率误差放大器的低功耗LDO设计

本文设计了一种具有低静态电流的低压差线性稳压器(LDO).针对传统LDO在低静态电流下瞬态响应不足的问题,电路中的误差放大器采用两个共栅差分跨导单元交叉耦合连接进行设计,提高其压摆率;利用体偏置运放改变功率管的阈值电压实现功率管在不同负载的快速切换;同时采用动态偏置对电路进行偏置减少过欠冲值.电路采用台积电(TSMC) 0.18μm互补金属氧化物半导体(CMOS)工艺进行设计,版图核心面积为220μm×140μm.仿真结果表明,该LDO在最小负载电流与最大负载电容的组合下相位裕度达到100度,消耗的静态电流仅为849nA.当负载电流在500 ns时间内从100μA到100 mA进行切换时,电路表现出良好的瞬态响应,其中过冲电压为220 mV,欠冲电压为225 mV.经过计算,品质因数(FOM)值为0.198 mV.     

一种快速瞬态响应的无片外电容型LDO电路设计

本文基于SMIC65 nm工艺,设计了一款快速瞬态响应的无片外电容型低压差线性稳压器(low dropout regulator,LDO).采用高增益跨导结构(OTA)的误差放大器,利用局部共模反馈结构(CFRFC),增加了放大器跨导率,提高了放大器的直流增益.同时,引入一个由电容耦合电流镜构成的瞬态检测电路,取代了传统LDO电路中的大电容,便于检测输出的跳变,增大对功率管的充放电能力,提高了环路瞬态响应速度,降低LDO环路的上/下冲电压.缓冲级采用了带电压负反馈的源级跟随器,在一定的静态功耗下,提高了动态电流,将次级点推到更高的频率,提高了电路相位裕度.仿真结果表明,输入电压为2～3 V时,该电路输出为1.2 V,最大负载电流为100 mA;当负载电流在0～100 mA时,LDO输出的最大过冲电压和欠冲电压为23 mV和27 mV,并且在低频时有较高的电源抑制比.     

一种低静态电流瞬态增强的无电容型LDO设计

基于推挽式结构能提高运算放大器压摆率的特性,设计了一款静态电流低、内含推挽式AB类放大器的无电容型低压差线性稳压器(LDO)。通过优化,改善了LDO的瞬态响应性能,与传统的LDO相比,所提出的无电容型LDO的静态电流明显减小。采用SMIC 0.18 μm CMOS工艺模型,利用Cadence工具对电路进行仿真验证。仿真结果表明,当输入电压为1.4~4 V时,优化后LDO的输出电压为1.2 V,静态电流为5.2 μA,最大负载电流达到100 mA,线性调整率为0.016%,负载调整率为0.67%,下过冲为157 mV,上过冲为121 mV,建立时间为1.5 μs。优化后电路瞬态响应性能改善了约50%,版图面积约为0.017 mm²。     

一种快速瞬态响应的无片外电容LDO

设计了一种快速瞬态响应的无片外电容低压差线性稳压器(LDO)。采用具有摆率增强作用的缓冲级电路,可以在不额外增加静态电流的同时检测输出端电压,在负载瞬间变化时增大功率器件栅极电容的充放电电流。缓冲级电路还引入了简单的负反馈技术,增加了环路的相位裕度。采用SMIC 180 nm的CMOS工艺进行设计和仿真。仿真结果表明,当输入电压为1.4~5 V时,该LDO的输出电压为1.2 V,最大负载电流为300 mA; 负载电流在1 mA和300 mA间变化时,最大过冲电压为76.5 mV,响应时间仅为1.5 μs。     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

一种低静态电流、高稳定性的LDO线性稳压器

该文提出了一种低静态电流、高稳定性低压差(LDO)线性稳压器。LDO中的电流偏置电路产生30nA的低温度漂移偏置电流,可使LDO的静态工作电流降低到4A。另外,通过设计一种新型的动态Miller频率补偿结构使得电路的稳定性与输出电流无关,达到了高稳定性的设计要求。芯片设计基于CSMC公司的0.5m CMOS混合信号模型,并通过了流片验证。测试结果表明,该稳压器的线性调整和负载调整的典型值分别为2mV和14mV;输出的最大电流为300mA;其输出压差在150mA输出电流,3.3V输出电压下为170mV;输出噪声在频率从22Hz到80kHz间为150VRMS。     

基于动态频率补偿的LDO电路设计

文中提出了一种基于动态频率补偿技术的LDO电路。通过添加电压缓冲器,提高了LDO的环路增益和瞬态响应特性。该电路通过电流镜采样调整管电流,使主极点频率与第三极点频率随负载电流的改变而产生相同倍数的变化,克服了LDO零极点随负载变化而导致环路稳定性变差的问题。文中设计采用中电二十四所HC12.BJT工艺,利用Spectre仿真工具进行仿真,研究了不同负载电流下该LDO的频率特性及其稳定性问题。仿真结果表明,该电路在10 μA~100 mA负载电流的变化范围内,LDO环路的相位裕度保持在50°~70°之间,证明提出的LDO调整器具有良好的稳定性。     

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.     

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out(LDO) regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV(0.7%) overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.     

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces V_OUT offset at medium to heavy load to counteract the V_OUT drop, which is caused by I_LOAD increase. Hence, transient performances of LDO and V_OUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with I_LOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the V_OUT drop between light load and full load reduces to 0.16 mV.     

一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.