以聚酰亚胺为绝缘层的并五苯场效应晶体管

报道了以聚酰亚胺(polyimide)作为绝缘层,并五苯作为活动层的一种全有机场效应晶体管.利用原子力显微镜(AFM)分析了聚酰亚胺薄膜及其表面并五苯薄膜的形貌;采用顶电极接触结构,测量出其场效应晶体管的输出特性曲线,并得出其场效应迁移率为0.079m2/(V·s),开关电流比约为104.     

以聚苯乙烯为绝缘层的C（60）场效应晶体管

研究制备了以聚苯乙烯(polystyrene)作为绝缘层,富勒烯C60为半导体有源层的一种全有机n型场效应晶体管.利用原子力显微镜(AFM)分析了聚苯乙烯薄膜及其表面C60薄膜的形貌.电学特性测试结果表明器件性能优良,场效应电子迁移率达到1.05cm2/V·s,开关比为9.4×105.     

ITO作为源漏电极的有机场效应晶体管

报道了一种OFET,它采用ITO作为源漏电极,聚酰亚胺为绝缘层,CuPc为半导体层.实验结果表明,该器件具有明显的场效应性质,性能较好,载流子迁移率和开关比分别达2.3×10-3 cm2/V.s、800,表明ITO是一种合适的、有前途的p型OFET源漏极材料.为此,本文对由电极材料和半导体材料间形成的接触电阻对OFET性能影响进行了分析.     

多壁碳纳米管/α-六噻吩双层OTFT气体传感器的制备及特性分析

以多壁碳纳米管(multi-walled carbon nanotubes,MWCNTs)和α-六噻吩(α-sexithiophene,α-6T)双层膜作为有源层,二氧化硅(SiO2)为绝缘层,钛/金(Ti/Au)作为电极,制备了沟道宽长比为640的有机薄膜晶体管(organic thin-film transistors,OTFT)气体传感器。测试了该传感器对痕量二氧化氮(NO2)气体的实时响应特性,并分析了NO2气体对OTFT传感器阈值电压、载流子迁移率等多参数的影响。研究结果表明,基于MWCNTs/α-6T的OTFT器件有较好的电学特性,载流子迁移率为3.0×10-2cm2/V·s;OTFT传感器对NO2气体具有较高的响应率,响应和恢复时间短,能检测(0.2~1)×10-6的痕量NO2气体,且具有良好的重复性;同时可以利用阈值电压和载流子迁移率等多参数来表征响应结果。形貌分析结果表明双层敏感膜的特殊形貌有利于提高器件的气敏性能。     

电子纸显示ITO电极保护层研究及其性能表征

为了避免电化学反应对电子纸显示电极和显示材料的损坏，用PVA（聚乙烯醇）、PET（聚酯）和PI（聚酰胺）等惰性高分子材料对ITO（氧化铟锡）薄膜电极进行了修饰，并通过原子力显微镜、电化学工作站以及红外、紫外可见光光谱分析等手段对修饰效果进行了研究。通过红外光谱和电化学工作站，研究了金属络合染料在电极上发生的电化学反应，通过紫外可见吸收光谱，研究了染料和颜料在电极保护层上的吸附与染色。试验结果表明，PI在ITO薄膜玻璃电极上粘接牢固，涂层致密，绝缘效果良好，能够有效地避免显示材料在电极上的电化学反应。     

非晶硅TFT栅界面层氮化硅薄膜性能的研究

采用傅里叶变换红外光谱仪、椭偏仪和YAF-5000M等测试仪器，对薄膜晶体栅界面层的键结构及含量、光学性能、物理性能以及晶体管导电性能进行分析研究。重点讨论了键含量与薄膜禁带宽度和介电常数的关系。结果表明：提高栅界面层N—H键含量（或减少Si-H键含量）能提高光禁带宽度和相对介电常数。栅界面层能改善非晶氮化硅薄膜和非晶硅薄膜的界面性能，提高薄膜晶体管的稳定性和场效应迁移率。     

a—SiTFT复合栅绝层用阳极氧化Ta2O5的研究

研究了Ｔａ的阳极氧化反应动力学，用自制装置有效地控制用于非晶硅薄膜晶体管（ａ－ＳｉＴＦＴ）的复合栅绝缘层Ｔａ２Ｏ５厚度，膜质均、性能优良，使用复合栅绝缘层Ａ－ＳｉＴＦＴ的开启电压（ＶＴ）控制中３－５Ｖ之间，开关电流比（Ｉｏｎ／ｏｆｆ）大于１０＾７，场效应迁移率为０．９６ｃｍ＾２／Ｖ．Ｓ。     

a—Si TFT复合栅绝缘层用阳极氧化Ta_2O_5的研究

研究了Ｔａ的阳极氧化反应动力学用自制装置有效地控制用于非晶硅薄膜晶体管（ａ─ＳｉＴＦＴ）的复合栅绝缘层Ｔａ２Ｏ５厚度，膜质均匀、性能优良，使复合栅绝缘层ａ─ＳｉＴＦＴ的开启电压（ＶＴ）控制在３─５Ｖ之间，开关电流比（Ｉ（ｏｎ）／Ｉ（ｏｆｆ））大于１０７，场效应迁移率为０．８６ｃｍ２／Ｖ·Ｓ．     

P型硅并五苯有机场效应晶体管的研制

以P＋＋硅为衬底，热生长SiO2为栅绝缘层，真空蒸发有机半导体材料并五苯作为有源层，射频磁控溅射金作为源、漏电极，成功制作了底接触式并五苯有机场效应晶体管（OFETs）。测试表明在源漏电压为70V时，器件的载流子迁移率μ为：0．31cm^2/V.s。     

采用真空镀膜制备的叠层结构有机场效应晶体管的研究

本文报道了一种叠层结构有机场效应管,它有别于一般的顶接触式和底接触式结构OFET.该器件采用真空镀膜制备,以SiO2作为绝缘层,酞菁铜CuPc作为沟道层.测量出其输出特性曲线,可看见较明显的场效应特性.对器件温度特性的研究表明,漏极电流随着温度的升高而增大.XRD分析表明,在Si/SiO2和Si/SiO2/Al两种衬底上蒸镀制备的CuPc薄膜呈多晶结构,且两种衬底上的CuPc薄膜晶粒尺度大致相等.     

Three-dimensional electrostatic effects of carbon nanotube transistors

We explore the three-dimensional (3-D) electrostatics of planar-gate carbon nanotube field-effect transistors (CNTFETs) using a self-consistent solution to the Poisson equation with equilibrium carrier statistics. We examine the effects of the gate insulator thickness and dielectric constant and the source/drain contact geometry on the electrostatics of bottom-gated (BG) and top-gated (TG) devices. We find that the electrostatic scaling length is mostly determined by the gate oxide thickness, not by the oxide dielectric constant. We also find that a high-k gate insulator does not necessarily improve short-channel immunity because it increases the coupling of both the gate and the source/drain contact to the channel. It also increases the parasitic coupling of the source/drain to the gate. Although both the width and the height of the source and drain contacts are important, we find that for the BG device, reducing the width of the 3-D contacts is more effective for improving short channel immunity than reducing the height. The TG device, however, is sensitive to both the width and height of the contact. We find that one-dimensional source and drain contacts promise the best short channel immunity. We also show that an optimized TG device with a thin gate oxide can provide near ideal subthreshold behavior. The results of this paper should provide useful guidance for designing high-performance CNTFETs.     

Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO ₂ gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source C_GS and gate to drain C_GD capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire     

High mobility top-gated poly(3-hexylthiophene) field-effect transistors with high work-function Pt electrodes

We report high-performance top-gated organic field-effect transistors (OFETs) with regio-regular poly(3-hexylthiophene) (rr-P3HT). The high charge carrier mobility in rr-P3HT FETs (0.4 cm²/Vs) was achieved due to the relatively low contact resistance and high crystallinity of rr-P3HT films. The contact resistance was controlled mainly through the use of high work-function platinum (Pt) (5.6 eV) for the charge injection electrode and a top-gate, bottom-contact geometry that enabled an enhanced current injection via current crowding in the staggered device structure. Moreover, the top-gate configuration provided improved device stability in air ambient conditions via the presence of a gate dielectric and gate electrode on top of the organic semiconductor.     

Study of surface-modified PVP gate dielectric in organic thin film transistors with the nano-particle silver ink source/drain electrode

We have fabricated the flexible pentacene based organic thin film transistors (OTFTs) with formulated poly[4-vinylphenol] (PVP) gate dielectrics treated by CF4/O2 plasma on poly[ethersulfones] (PES) substrate. The solution of gate dielectrics is made by adding methylated poly[melamine-co-formaldehyde] (MMF) to PVP. The PVP gate dielectric layer was cross linked at 90 degrees under UV ozone exposure. Source/drain electrodes are formed by micro contact printing (MCP) method using nano particle silver ink for the purposes of low cost and high throughput. The optimized OTFT shows the device performance with field effect mobility of the 0.88 cm2/V s, subthreshold slope of 2.2 V/decade, and on/off current ratios of 1.8 x 10(-6) at -40 V gate bias. We found that hydrophobic PVP gate dielectric surface can influence on the initial film morphologies of pentacene making dense, which is more important for high performance OTFTs than large grain size. Moreover, hydrophobic gate dielelctric surface reduces voids and -OH groups that interrupt the carrier transport in OTFTs.     

Electrical characteristic analysis using low-frequency noise in low-temperature polysilicon thin film transistors

This study carried out an electrical characteristic analysis using low-frequency noise (LFN) in top gate p-type low-temperature polysilicon thin film transistors (LTPS TFTs) with different active layer thicknesses between 40 nm and 80 nm. The transfer characteristic curves show that the 40-nm device has better electrical characteristics compared with the 80-nm device. The carrier number fluctuation, with and without correlated mobility fluctuation model in both devices, has modeled well the measured noise. On the other hand, the trap density and coulomb scattering in the 40-nm device are smaller compared with the 80-nm device. To confirm the effectiveness of the LFN noise analysis, the trap densities at a grain boundary are extracted using in both devices the similar methods of Proano et al. and Levinson et al. That is, coulomb scattering, caused by the trapped charges at or near the interface, has a greater effect on the device with inferior electrical properties. Based on the LFN and the quantitative analysis of the trap density at a grain boundary, the interface traps between the active layer and the gate insulator can explain the devices' electrical degradation.     

Amorphous oxide channel TFTs

Thin film transistors (TFTs) using amorphous oxides of post-transition metals: indium, gallium, and zinc for the channel materials are fabricated with radio-frequency magnetron sputtering methods for the deposition of the channel and the gate insulator layers, at room temperature with no high-temperature post-deposition annealing process. The TFTs operate as n-channel field-effect transistors with various structures of top/bottom gate and top/bottom source-and-drain contact including the inverse-stagger types, and with various materials for the gate insulators, the electrodes, and the substrates. The TFTs having smoother channel interfaces show the better performance at the saturation mobility beyond 10 cm² V^− 1 s^− 1 and the on-to-off current ratio over 10⁸ than the rough channel interfaces. The ring oscillator circuits operate with five-stage inverters of the top-gate TFTs or the inverse-stagger TFTs. Organic light-emission diode cells are driven by a simple circuit of the TFTs. It is also found by a combinatorial approach to the material exploration that the TFT characteristics can be controlled by the composition ratio of the metals in the channel layers. The amorphous oxide channel TFTs fabricated with sputtering deposition at low temperature could be a candidate for key devices of large-area flexible electronics.     

Investigation of self-assembled monolayer treatment on SiO2 gate insulator of poly(3-hexylthiophene) thin-film transistors

We have investigated self-assembled monolayer (SAM) treatment on SiO₂ gate insulator of poly(3-hexylthiophene) (P3HT) thin-film transistor (TFT), and demonstrated a correlation between mobility and surface free energy of the insulator. The device with lower surface free energy shows higher mobility. The docosyltrichlorosilane (DCTS)-treated device exhibits the best performance among the various SAM-treated devices examined. Field-effect mobility, on/off ratio and threshold voltage of the DCTS-treated P3HT TFT were 0.015 cm²/Vs, >10⁵ and −14 V, respectively.     

Optimization of single-gate carbon-nanotube field-effect transistors

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I/sub on//I/sub off/ ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I/sub on//I/sub off/ ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V/sub g/=V/sub d//2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.     

Contacting versus insulated gate electrode for Si nanoribbon field-effect sensors operating in electrolyte

Electric response to pH variations is employed to investigate Si nanoribbon field-effect transistors (SiNRFETs) operating in electrolyte with different gate configurations. For devices with a conducting gate electrode for direct metal-electrolyte contact, a well-defined electrode reaction leading to a stable electrode potential is essential for retaining a stable electrical potential of the electrolyte. However, noble metals such as Pt do not meet the stability requirement and consequently bring severe distortions to the electronic response. For devices with an insulated gate electrode relying on the principle of capacitive gate coupling, the capacitance between the gate electrode and the electrolyte should be made much larger than the gate capacitance established between the SiNR and the electrolyte. In this case, an efficient gate control as well as a high stability against external disturbances can be ensured. Further studies show that surface charging of the gate insulator is the main cause responsible for the pH response of the SiNRFETs. Hence, devices with different gate configurations give rise to a comparable pH sensitivity.     

Tunable Fröhlich polarons in organic single-crystal transistors

In organic field-effect transistors (FETs), charges move near the surface of an organic semiconductor, at the interface with a dielectric. In the past, the nature of the microscopic motion of charge carriers--which determines the device performance--has been related to the quality of the organic semiconductor. Recently, it was discovered that the nearby dielectric also has an unexpectedly strong influence. The mechanisms responsible for this influence are not understood. To investigate these mechanisms, we have studied transport through organic single-crystal FETs with different gate insulators. We find that the temperature dependence of the mobility evolves from metallic-like to insulating-like with increasing dielectric constant of the insulator. The phenomenon is accounted for by a two-dimensional Fr?hlich polaron model that quantitatively describes our observations and shows that increasing the dielectric polarizability results in a crossover from the weak to the strong polaronic coupling regime. This represents a considerable step forward in our understanding of transport through organic transistors, and identifies a microscopic physical process with a large influence on device performance.