SI GaAS中S~+注入的电学特性

本文研究了经常规热退火和快速热退火后SIGaAs中S~+注入的电学特性.热退火后,GaAs中注入S~+的快扩散和再分布不决定于S~+或砷空位V_(AS)的扩散而决定于离子注入增强扩散.使用快速热退火方法能抑制注入S~+在GaAs中的增强扩散,明显减小S~+的再分布,可以获得适合于制造GaAs MESFET器件的薄有源层.     

GaAs离子注入Si的快速热退火

一、引言 GaAs集成电路的发展与在半绝缘衬底上进行外延的外延层或进行出子注入形成导电沟道的质量和接触区的常规工艺有关。由于在器件和电路制造过程中,存在外延材料成本高以及难以制成浅结等问题,所以,近年来,国际上广泛开展了离子注入高纯半绝缘GaAs来制造砷化镓场效应晶体管和进行GaAs单片集成电路的研究。离子注入具有掺杂浓度可控,均匀性和重复性好的特点,以及与其它工艺组合灵活等优点。但注入样品必须在高温(≥800℃)下退火,以消除注入损伤和电激活掺杂剂。在通常的炉子退火(850℃,30′)条件下,由于GaAs表面的As原子易挥发,使得GaAs的化学计量比失配,造成器件特性变坏。使用包封层,虽然解决了As原子的挥发问题,但由于包封层与样品之间的热膨胀系数不匹配,在高温下存在热应力,进而引起膜皱曲甚至脱落,样品表面层中该热应力引入缺陷杂质对材料特性产生影响。目前,国外研究较多的是快速热退火(RTA)。这种方法由于退火时间短,退火温度高,更有利于复杂缺陷的消除,激活层电特性好,注入杂质和衬底杂质的互扩散小,不需包封层,因此消除了包封层和衬底界面处的应力和组分互扩散,而且退火时不涉及AsH_3这样的有毒气体。     

硼离子注入退火过程对表面迁移率及薄层电阻的影响

本文利用与退火条件有关的离子注入杂质分布,得到了在硅中硼离子注入退火条件对载流子表面迁移率的影响。还得到了硼离子注入薄层电阻与注入条件及退火情况的关系。在这些关系中,注入剂量对迁移率及薄层电阻有最主要的影响。这些结果可在设计和制造VLSI中用以确定工艺条件。     

适用于VLSI工艺的多功能二维离子注入模拟器FUTIS

本文改进和发展了硅中二维离子注入、离子注入退火及高剂量氧注入分布模型;处理了多次注入、多层掩蔽、多种材料掩蔽及多种掩模边缘;在此基础上给出了适用于VLSI工艺的多功能、实用化二维离子注入模拟器FUTIS。通过与其它工艺模型、模拟器及实验比较,表明FUTIS在精度上有明显改进,在功能上有很大扩展,是一种能适应当今VLSI工艺发展要求的先进的离子注入模拟器。     

砷化镓中的离子注入

在半导体器件制造工艺中,离子注入技术日益广泛地得到应用。特别是在硅器件中,利用离子注入制作MOS器件和双极晶体管以及MOS集成电路等都已投入大量生产。预计在1975～1980年将实现全注入MOS及双极大规模集成电路。在化合物半导体中的离子注入技术也在进行广泛研究,特别是在砷化镓方面的研究已取得较大成果,正逐步应用于器件制造中。     

离子注入白光退火特性

本文研究了离子注入后碘钨灯的退火效果;测量了离子注入和瞬态退火样品的电阻率、迁移率、电激活率和注入层电阻率的均匀性;用背散射和扩展电阻仪得到As浓度和载流子浓度分布;获得了制备浅结的工艺条件。用超高压电镜分析了注入层的剩余缺陷。同热退火比较表明白光退火技术更适于超大规模集成电路的微细加工工艺的要求。     

非相干光退火技术与非晶硅薄膜的固相外延

本文介绍了一种新的退火技术——非相干光脉冲加热退火。它与激光退火技术相比,效率高,设备简单;与传统热退火相比,对离子注入杂质的激活率高,≈100％,不引起杂质再分布,且能有效地避免离子注入损伤层对重金属离子的收集,在超大规模集成电路工艺中有着多方面应用的可能性。作者应用这一退火技术于LPCVD非晶硅薄膜的再结晶研究。用RBS结合电子沟道技术研究了再结晶化的动力学过程。实验发现,在硅衬底上淀积的非晶硅薄膜(1600(?))能在600℃、35秒和700℃、15秒时间内完成再结晶化过程,结晶化结构属柱状。     

离子注入掺杂热再分布的分析计算

本文对离子注入杂质的熟再分布过程提出了两种分析手段，其一是已知热再分布的工艺条件，求解扩散方程得到最终杂质分布的解析结果；其二是已知再分布后杂质分布的边界条件，采用牛顿—拉夫逊。蒙特卡罗计算方法，求得最终杂质浓度分布；并给出了CMOS集成电路中离子注入p阱的计算结果。     

离子注入掺杂热再分布的理论分析

本文对离子注入搀杂杂质分布的热再分布过程提出了两种分析手段。其一是已知热再分布的具体过程,通过求解扩散方程得到了杂质最终分布的解析解;其二是已知热再分布最终杂质分布的某个边界条件,本文提出了有效杂质总量守恒模型,并采用牛顿-拉夫逊,或蒙特卡罗计算机数值方法,可求得最终的杂质分布。文中最后给出了CMOS工艺中离子注入P阱的计算结果。     

AS离子注入硅化钛自对准MOS器件技术研究

本工作研究了同时形成polycide栅,源/漏硅化钛接触和浅PN结的MOS器件制造技术。实验结果表明,通过硅化钛薄膜注入As,并利用NH_3等离子体辅助热退火(NPTA)工艺,可制备性能良好的MOS晶体管。以注入杂质的硅化钛薄膜作为杂质源,在一次高温退火过程中同时完成杂质的再分布和低电阻率硅化钛的形成,得到结深小于0.1μm,硅化钛电阻率24μΩ·cm。NPTA退火工艺有效地抑制了Ti/Si和Ti/poly-Si固相反应过程中硅化钛的横向生长,从而获得了自对准程度很高的硅化钛接触和互连。     

Drive-Current Enhancement in Ge n-Channel MOSFET Using Laser Annealing for Source/Drain Activation

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD$hboxHfO_2$has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation.     

Low-temperature processing of antimony-implanted silicon

It is shown for the first time that antimony-implanted silicon produces the highest electrical activation (90%) with low resistivity (<200 ohms/square) following low-temperature processing. Thus, annealing at 650°C produces the best results for antimony, whereas for arsenic, it is necessary to anneal at temperatures above 1000°C to get optimum results. Silicon was implanted with antimony at 12 keV and 40 keV and doses of 8.5×10¹⁴ cm⁻² and 4×10¹⁴ cm⁻², respectively, and arsenic at equivalent energies and doses. The electrical data from both implants are compared in order to identify the process conditions require to obtain optimum results. It is demonstrated that annealing below 800°C produces electrical profiles with no measurable diffusion of the antimony, but higher temperature anneals produce significant diffusional broadening.     

The simulation of epitaxy, sublimation, and annealing processes in a 3D silicon surface layer

The Monte Carlo model for simulating epitaxy, sublimation, and annealing of the (111) surface of a diamond-like crystal is developed. The model accounts for the so-called overhanging structures and allows one to consider a 3D surface layer with a complex structure and volume comprising as many as 10⁷ atom sites. The initial stage of epitaxial growth on smooth as well as on porous surfaces and the annealing of both step-containing and porous surfaces are simulated. The effect of Schwoebel barriers on the formation of compact 3D islands during epitaxy is suggested as a possible kinetic mechanism for quantum-dot formation. The sublimation behavior of monatomic steps on the (111) surfaces of a diamond-like crystal is also studied.     

Enhancing the Charge Transport in Solution‐Processed Perylene Di‐imide Transistors via Thermal Annealing of Metastable Disordered Films

The introduction of side chains in π‐conjugated molecules is a design strategy widely exploited to increase molecular solubility thus improving the processability, while directly influencing the self‐assembly and consequently the electrical properties of thin films. Here, a multiscale structural analysis performed by X‐ray diffraction, X‐ray reflectivity, and atomic force microscopy on thin films of dicyanoperylene molecules decorated with either linear or branched side chains is reported. The substitution with asymmetric branched alkyl chains allows obtaining, upon thermal annealing, field‐effect transistors with enhanced transport properties with respect to linear alkyl chains. Branched chains induce molecular disorder during the film growth from solution, effectively favouring 2D morphology. Post‐deposition thermal annealing leads to a structural transition towards the bulk‐phase for molecules with branched chains, still preserving the 2D morphology and allowing efficient charge transport between crystalline domains. Conversely, molecules with linear chains self‐assemble into 3D islands exhibiting the bulk‐phase structure. Upon thermal annealing, these 3D islands keep their size constant and no major changes are observed in the organic field effect transistor characteristics. These findings demonstrate that the disorder generated by the asymmetric branched chains when the molecule is physisorbed in thin film can be instrumental for enhancing charge transport via thermal annealing.     

目标表面BRDF统计建模中的遗传模拟退火算法

结合基本遗传算法与模拟退火算法,构造出了新的具有全局搜索优化特性的遗传模拟退火算法.根据卫星表面BRDF实验数据和统计模型,引用遗传模拟退火算法,获得样片BRDF模型参数的优化估计,从而获得了三维空间的BRDF分布,其优化参数后的模型在另一部分数据上也得到了很好的吻合验证.     

电子和中子辐照n型6H-SiC的光致发光谱

对用电子能量为1.7,0.5和0.4MeV的电子辐照和中子辐照后的n型6H-SiC样品进行低温光致发光研究.对于Ee≥0.5MeV电子辐照和中子辐照后的样品,首次发现了位于478.6/483.3/486.1n m的S1/S2/S3谱线.对样品进行热退火研究表明S1/S2/S3谱线在500℃下消失,而退火温度高于700℃时D1中心出现.考虑到产生C空位和Si空位所需的位移阈能以及热退火行为,说明S1/S2/S3为初级Si空位初级缺陷,而D1中心为二次缺陷.     

混合D2D蜂窝网络中基于模拟退火算法的资源调度策略

D2D通信是未来5G网络中一种近距离直通通信方式,在通信过程中,信息直接由发送端传给接收用户,而不需要经过基站的转发.在传统蜂窝网络中引入D2D通信可以极大地提升系统的总吞吐量、增大频谱资源的利用率以及降低发射终端的功耗.主要介绍了一种适用于混合D2D蜂窝网络中的资源分配方法,通过拉格朗日乘子法结合模拟退火算法实现频谱资源的分配,提出一种同时考虑信道容量和能耗的基于模拟退火算法的资源调度策略.本算法在维也纳仿真平台上经仿真验证,相比于传统贪婪优化算法,可以明显增大系统总吞吐量和频谱资源利用率.另外,算法中采用了分布式资源调度方法,D2D用户根据算法步骤自行搜索适合的目标信道并计算其发射功率,可以有效减少基站的信令开销.     

10位双极数模转换器的电离辐射效应

研究了国产互补双极工艺生产的数模转换器(D/A转换器)在不同偏置和不同剂量率条件下的电离辐射效应及退火特性。研究结果表明:D/A转换器对偏置条件和辐照剂量率都很敏感。大剂量率辐照时,电路功能正常,各功能参数变化较小;而在低剂量率辐照情况下,各参数变化显著,超出器件允许范围,器件功能失效。因此,D/A转换器表现出明显的低剂量率辐射损伤增强效应(ELDRS)。零偏时,D/A转换器功能参数损伤变化更加严重。最后,结合边缘电场效应和空间电荷模型对这种不同偏置和剂量率条件下的损伤机理进行了初步的探讨。     

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

The surface electron mobility of HfO/sub 2/ NMOSFETs with a polysilicon gate electrode was studied in terms of the effects of high-temperature forming gas (FG) annealing. The high-temperature FG annealing significantly improved the drive current or the surface electron mobility of the NMOSFETs. Improvements were also observed in the subthreshold swings and the C-V characteristics, indicating a reduction in interfacial state density (D/sub it/). The D/sub it/ reduction was quantitatively confirmed by charge pumping current measurements. The mobility enhancement was achieved without degrading the equivalent oxide thickness (EOT) or gate leakage current. Different surface preparations, such as NH/sub 3/ or NO annealing, were explored to examine their effects on the NMOSFET performance. Mobility enhancement due to high-temperature FG annealing was also observed on these samples. Whereas NH/sub 3/ surface nitridation was effective in scaling EOT, the NO-annealed sample exhibited the highest mobility. Similar improvements were also observed on HfO/sub 2/ PMOSFETs, in terms of subthreshold swings, drive current, and surface hole mobility.     

Diffusional creep induced stress relaxation in thin Cu films on silicon

The results of stress measurements during annealing of thin copper films deposited on 100 μm Si substrates are presented. The stress in thin films was determined by using an optical system for curvature measurements. The annealing experiments were done during thermal cycles of heating and cooling procedures from room temperature up to 400 °C with a rate 10 °C/min. The total thickness of thin films was between 20 and 100 nm. The obtained results showed that the difference between the end and the initial values of the ratio of force to width increases with the thickness of the samples. The initial linear shape of the temperature-stress plots reaches higher temperature values with an increase in film thickness. In order to explain the observations, the dependence of stress on temperature was calculated using the rate of Coble creep. It was found that the theoretical curves reveal the same features as the experimental data. It was concluded that diffusional creep mechanism dominates for thin film of thickness below 100 nm.