CMOS单元电路版图的自动设计

本文描述了ＣＭＯＳ单元电路版图自动设计程序是自动电路版图设计系统的一个组成部分，它通过一列变换，将单元电器描述翻译成单元电路版图的几何描述。其特点是允许单元内多端口线网布和允许在单元四周指定端口，并对单元电路版图进行优化，因此，只要输入单元电路描述，便可自动产生单元电路的版图文件。     

PSpice6.2程序用于电路噪声计算的方法

ＰＳｐｉｃｅ６．２（窗口版）是国际著名的通用电路分析程序，本文介绍了应用该程序对电路进行噪声计算的方法，这在国内尚属首例。文中给出用ＰＳｐｉｃｅ６．２程序计算的典型电路噪声，证明这种方法在分析复杂电路的噪声时方便、简单、准确。     

多值开关级代数在MOS电路形式验证中的应用

本文讨论了ＭＯＳ电路多值开关级代数表达式的三种标准结构，给出了将多值开关级表达式转换成布尔表达式的定理，基于这些理论，提出了ＭＯＳ电路开关级形式验证的一种方法。     

电路在线测试技术及应用

电路在线测试技术是一种电路板的计算机自动测试技术。本文以意大利的自动测试设备Ｓ２０ （Ｓ２０ＡＴＥ）为例， 阐述了这种技术的基本原理， 同时介绍了Ｓ２０ＡＴＥ的系统结构和编程使用办法。     

调频电路灵敏度的PSPICE辅助分析

提出了应用ＰＳＰＩＣＥ程序辅助分析和设计电子线路的方法，给出了使用ＰＳＰＩＣＥ程序对调频电路进行模拟的实例，列出了灵敏度分析的上体应用程序。     

电路在线测试技术及应用

电路在线测试技术是一种电路板的计算机自动测试技术。本文以意大利的自动测试设备Ｓ２０（Ｓ２０ＡＴＥ）为例，阐述了这种技术的基本原理，同时介绍了Ｓ２０ＡＴＥ的系统结构和编程使用办法。     

CMOS神经元（I）：基本神经元电路模型

本文给出了一种新的ＣＭＯＳ技术实现的连续时间神经元电路模型，讨论其突触权值的调节和细胞体参数的设置问题，计算机模拟表明，该模型具有生物神经元时空整合特性和神经计算功能。     

MCS—51单片机控制的DTMF信号发送／接收电路

ＭＣＳ—５１单片机控制的ＤＴＭＦ信号发送／接收电路郑州大学廖天河，李亚平１ＳＲＭＦ发送电路双音多频信号ＤＴＭＦ的发送电路，在单片机８０３１的控制下，以ＭＶ５０８７为核心，外接标准晶振（３．５８ＭＨＺ）和用８中取２标准键盘构成的４Ｘ４键盘矩阵等组成，如...     

CMOS专用定时电路(LC4767)工艺研究

主要介绍了专用ＣＭＯＳ电路中采用齐纳二极管降低并稳定电压,保证电路的正常工作并降低功耗,拓宽了ＣＭＯＳ混合电路的应用范围。     

单片机系统的电平转换技术

由于不同逻辑电路的逻辑电平有效地区间不一致，导致不同的逻辑电路一般不能直接连接使用，它们之间存在逻辑电平转换问题，在微机测控系统中，一般用ＴＴＬ电路作为基本电路元件，本文针对单片机系统中常用的ＣＭＯＳ，ＨＴＬ芯片及通用串行通信接口，对ＴＴＬ电路与它们之间相互连接时的电平转换进行了讨论，并给出了对应的接口电路。     

一种电池供电的采煤机启动预警电路设计

介绍了一种电池供电的采煤机启动预警电路的软、硬件设计方案,电路调试方法,调试过程中出现的问题及优化方法。该电路采用12 V充电电池作为系统电源,由MSP430F149单片机控制采煤机机身上电的预警过程,并且实时监控电池电量;如果单片机检测到的电池电压低于程序预设的低电压阈值,则驱动LED发出闪烁提醒信号,提醒用户给系统电池充电;整个电路在不用时处于低功耗模式,以延长使用时间。经过调试及优化,该电路程序运行正确,静态功耗仅为0.2 mA,满足低功耗设计要求。     

组合电路功耗敏感性统计分析

功耗已经成为集成电路设计的一个十分重要的问题．对于一个给定的电路,其功耗是与输入密切相关的,即对于不同的输入向量集,同一电路可能会有不同的功耗．功耗敏感性定义了由于原始输入的改变而引起的功耗变化特性．文中给出了基于信号置1概率和跳变率传输特性的功耗敏感性分析方法,并详细阐述了它在无时延动态功耗估计和静态功耗估计中的应用．实验结果表明,它在保证了较好精度的条件下,大大降低了估计时间;另外,这一方法还可以应用于时延动态功耗估计、在特定向量集上的动态及静态功耗估计,并且在一定程度上为低功耗设计提供参考．     

同步整流DC/DC升压芯片中驱动电路的设计

在DC／DC转换芯片中，为了保证功率开关管及时导通和截止，需要设计专门的驱动电路。本文设计了同步整流驱动电路，通过引入负跳沿延时单元，消除了CMOS瞬态短路导通现象，降低了功耗，保护了输出级。HSPICE仿萁表明，驱动电路延时小于14ns，能满足较高开关频率的要求；同时，开关转换时的尖峰电流减小了56％，功耗也降低了19．3％。     

High performance nanocomparator: a quantum dot cellular automata-based approach

Quantum dot cellular automata (QCA) are emerging nanotechnology that offers few significant advantages like faster speed, higher circuit density, and lower power dissipation. Comparator is a fundamental and essential block in QCA logic circuit family. In this article, a single-layered and straightforward design of a QCA-based one-bit magnitude comparator has been proposed. The proposed design is 6.38%, 6.67% and?~?10% more efficient in cell complexity, cell area and total area measurement, respectively, in comparison to prior reported designs. Furthermore, the energy dissipation of the proposed circuit has been calculated using QCADesigner-E and QCAPro tools to check the energy efficiency of the proposed circuit. The total energy dissipation of the reported magnitude comparator is 19.50 meV when measured using the QCADesigner-E tool. Similarly, according to the QCAPro tool, it has?~?71% less energy dissipation than the existing designs.

     

Novel low power reversible binary incrementer design using quantum-dot cellular automata

This paper demonstrates the design of n-bit novel low power reversible binary incrementer in Quantum-Dot Cellular Automata (QCA). The comparison of quantum cost in quantum gate based approach and in QCA based design agreed the cost efficient implementation in QCA. The power dissipation by proposed circuit is estimated, which shows that the circuit dissipates very low heat energy suitable for reversible computing. All the circuits are evaluated in terms of logic gates, circuit density and latency that confirm the faster operating speed at nano scale. The reliability of the circuit under thermal randomness is explored which describes the efficiency of the circuit.     

单片机智能仪表系统的低功耗设计

本文介绍了在智能仪表设计中一些经试用证明可有效降低系统功耗的电路设计方法和软件编制措施。     

基于MSP430F149与Si4432的无线传感器网络的实现方法

介绍了基于MSP430F149与Si4432的无线传感器网络节点的硬件及软件设计方法,给出了主要的硬件电路和软件流程图,提出了一种简单易实现的低功耗自组织协议。实验证明,该无线传感器网络具有组网速度快、功耗低、抗干扰能力强、通信稳定可靠等特点,可应用于多个领域的信息探测,具有广阔的市场前景。     

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic （ICPAL） based on fin-type field- effect transistor （FinFET） devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies（30-800 MHz） under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass- transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.     

A real-time QoE methodology for AMR codec voice in mobile network

This paper studies a general strategy to predict voice Quality of Experience （QoE） for various mobile networks. Particularly, based on data-mining for Adaptive Multi-Rate （AMR） codec voice, a novel QoE assessment methodology is proposed. The proposed algorithm consists of two parts. The first part is devoted to assessing speech quality of fixed rate codec mode （CM） of AMR while in the other one a adaptive rate CM is designed. Measuring basic network parameters that have much impact on speech quality, QoE can be monitored in rei time for operators. Meanwhile, based on the measurement data sets from real mobile network, the QoE prediction strategy can be implemented and QoE assessment model for AMR codec voice is trained and tested. Finally, the numerical results suggest that the correlation coefficient between predicted values and true values is greater than 90~0 and root mean squared error is less than 0.5 for fixed and adaptive rate CM.     

Asynchronous processor survey

Virtually all computers today are synchronous. As systems grow increasingly large and complex the clock can cause big problems with clock skew, a timing delay that can create havoc with the overall design. It can also increase the circuit silicon and power dissipation, which can affect overheating and power supplies. Computer architecture researchers are actively considering asynchronous processor design. Asynchronous architectures permit modular design. Each subsystem or functional block can be optimized without being synchronized to a global clock, which simplifies interfacing. Moreover, an asynchronous system exhibits the average performance of all the individual components, rather than the synchronous system's worst-case performance of a single component. Furthermore, asynchronous processors may yet prove to offer reduced power dissipation by inherently shutting down unused portions of the circuit. This article examines the key architecture issues that concern designers and compares six developmental asynchronous architectures: CAP, the Caltoch Asynchronous Processor; FAM, the Fully Asynchronous Microprocessor; NSR, the Nonsynchronous RISC; CFPP, the Counterflow Pipeline Processor; Strip, a Self-Assured RISC Processor; and Amulet 1