基于FPGA的DVB-S2通用LDPC编码器设计与实现

研究了一种用FPGA实现DVB-S2标准的LDPC码高速通用编码器的设计方法.设计采用流水线技术和全并行结构相结合的方法,提高了编码效率.FPGA仿真结果和综合报告表明,设计的LDPC码编码器具有通用性,能够针对DVB-S2中两种码长、11种码率的LDPC码进行编码,且时钟频率达到了114 MHz,适用于DVB-S2标准.     

LDPC在DVB-S2中的应用

介绍了LDPC码,并基于DVB-S2中LDPC码分析了该类码的构造、编码及解码原理,同时给出DVB-S2中LDPC码的结构及仿真结果.     

DVB-S2标准LDPC码的算法研究和仿真

阐述了LDPC(Low Density Parity Check)码的基本原理,基于DVB-S2中LDPC码分析了该类码的构造、编码及译码原理,同时给出DVB-S2中LDPC码在码率为2/3、码长为16200bits时的仿真结果。仿真结果表明,在低信噪比情况下,该LDPC码仍然获得了令人满意的纠错效果,且在性能上的确优于其他码。随着技术的进步,相信LDPC编译码技术将在更多的领域得到应用。     

DVB-S2标准 LDPC码的算法研究和仿真

阐述了LDPC(Low Density Parity Check)码的基本原理,基于DVB-S2中LDPC码分析了该类码的构造、编码及译码原理,同时给出DVB-S2中LDPC码在码率为2/3、码长为16 200 bits时的仿真结果.仿真结果表明,在低信噪比情况下,该LDPC码仍然获得了令人满意的纠错效果,且在性能上的确优于其他码.随着技术的进步,相信LDPC编译码技术将在更多的领域得到应用.     

一种基于DVB-S2标准的LDPC缩短码

提出一种基于DVB-S2标准的LDPC缩短码,该码直接采用DVB-S2标准LDPC码的校验矩阵参数和编码算法,所提出的基于DVB-S2标准的LDPC缩短码无4环,具有良好的误码率性能,适用于移动数字电视系统.     

应用于新一代卫星数字电视的LDPC码浅析

主要介绍了应用于新一代卫星数字电视传输标准(DVB-S2)的LDPC码,稀疏的校验矩阵使得该码具有能够逼近香农极限的特性,并可在不太高的复杂度内实现译码.和积算法是LDPC码的通用译码方法,在实用码长和高斯白噪条件下进行了性能仿真.     

DVB—S2系统中LDPC译码器的实现

随着VLSI技术的发展,LDPC（Low Density Parity Check）码被确定为下一代数字卫星电视标准（DVB-S2）的信道编码方案。文中针对DVB—S2标准,分析了LDPC码的结构特点,给出了LDPC译码改进算法,从而降低了其实现的复杂度。同时通过算法仿真,验证了LDPC改进算法在低信噪比条件下的卓越性能和高速率的数据处理速度。     

基于非规则LDPC码的图像传输性能

LDPC码性能非常逼近香农极限且实现复杂度低,具有很强的纠错抗干扰能力,几乎适用于所有信道。在此采用DVB-S2标准中LDPC码的构造和编码方案,重点研究了LDPC码的译码原理,并将其用于加性高斯白噪声信道（AWGN Channel）图像的传输中。仿真结果表明在非规则LDPC码在低信噪比情况下,能为图像传输带来显著性能提高,且系统复杂度低,译码时延短。     

标准低密度奇偶校验码译码算法中量化结构

DVB-S2标准低密度奇偶校验码(LDPC)译码器在深空通信中面临着低复杂度、高灵活性及普适性方面的迫切需求。通过对LDPC译码算法中量化结构的研究,提出一种动态自适应量化结构的设计方法。该方法在常规均匀硬件量化的基础上,提出了修正化Min-Sum译码算法中的数据信息初始化及迭代译码的动态自适应量化结构,解决了DVB-S2标准LDPC码译码时存在的校验节点运算与变量节点运算之间的复杂度不平衡的问题,并由此提高了译码器的译码性能。实验证明,以DVB-S2标准LDPC码中码长为16 200,码率为1/2的为例,提供动态自适应量化结构与常规的均匀量化结构相比,节省硬件资源为4%。此外,动态自适应量化结构支持动态可配置功能,保证了DVB-S2标准LDPC译码器的灵活性及普适性。     

逼近Shannon限的LDPC码

LDPC码具备逼近Shannon限的优异性能，是当前学术界和工业界的研究热点。许多最新糊定的系统标准，如DVB-S2和IEEE802．10e，都采用了LDPC码，LDPC码在各个领域，包括广播电视领域，都将会有大发展。本文对LDPC码进行了系统性的介绍，以求读者获得概念性的了解。     

LDPC编码中大矩阵求逆及存储的一些方法

低密度奇偶校验(LDPC)码在CMMB、DVB-S2及地面数字电视国家标准(GB20600-2006)等标准中得到了广泛的应用,LDPC码在码长较长时优势才比较明显,而在进行编码运算时码长较长会遇到大矩阵求逆及存储方面的问题,就此提出一些大矩阵求逆及存储的方法,简化了LDPC编码运算时的复杂度.     

Faster-than-Nyquist signaling: on linear and non-linear reduced-complexity turbo equalization

In the framework of digital video broadcasting by satellite-second generation (DVB-S2), we analyze a faster-than-Nyquist (FTN) system based on turbo equalization and low-density parity-check (LDPC) codes. Truncated maximum a posteriori and minimum mean square error equalizers provide a reduced-complexity implementation of the FTN system. On the other hand, LDPC codes allow us to demonstrate attractive performance results over an additive white Gaussian noise channel while increasing spectral efficiency beyond the Nyquist rate and keeping a complexity comparable to that of a current DVB-S2 modem.     

一种新的终止LDPC迭代译码算法

在传统的卫星广播系统中,信道纠错通常采用BCH码级联LDPC码的方案以达到良好的误码率性能,例如DVB-S2系统。作为内码的LDPC码通常采用迭代译码,且迭代次数较高才能实现比较好的系统性能。借助BCH级联LDPC的结构,文中提出了将BCH检错嵌套进LDPC每一次迭代译码过程中的新的迭代译码结构。仿真结果表明,新算法以较低的BCH码检错运算复杂度换取了LDPC码迭代次数的明显下降,从而极大降低了迭代译码总体复杂度和译码时延,且整体纠错性能与原始LDPC译码后BCH纠错的算法相比基本保持不变。     

DVB-S2 LDPC Decoding Using Robust Check Node Update Approximations

Broadband satellite services to fixed terminals are currently offered in the forward link by the 2nd generation (2G) digital video broadcasting satellite (DVB-S2) standard. For this standard the use of powerful low-density parity-check (LDPC) error correcting codes has been adopted performing within approximately 1 dB from the Shannon capacity limit. This paper studies and compares for the first time in a systematic manner different approximation methods used in check node update computation of DVB-S2 LDPC decoding with the aim of reducing computational complexity. Various performance evaluation results are presented for a wide range of DVB-S2 parameters, such as LDPC codeword size, coding rate, modulation format and including several decoding algorithms. It is shown that the proposed check node update approximations have a robust behavior, i.e. the resulting performance is quite independent of the DVB-S2 modulation and coding parameters. It is further shown that these approximations perform very close to the optimal sum-product algorithm (SPA) in degradation, which is less than 0.2 dB. Despite this small degradation, the reduction in computational complexity compared to the optimal SPA is significant and can be as high as 40% in computational time savings.     

Implementation of a Flexible LDPC Decoder

Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.     

Efficient GPU and CPU-based LDPC decoders for long codewords

The next generation DVB-T2, DVB-S2, and DVB-C2 standards for digital television broadcasting specify the use of low-density parity-check (LDPC) codes with codeword lengths of up to 64800 bits. The real-time decoding of these codes on general purpose computing hardware is useful for completely software defined receivers, as well as for testing and simulation purposes. Modern graphics processing units (GPUs) are capable of massively parallel computation, and can in some cases, given carefully designed algorithms, outperform general purpose CPUs (central processing units) by an order of magnitude or more. The main problem in decoding LDPC codes on GPU hardware is that LDPC decoding generates irregular memory accesses, which tend to carry heavy performance penalties (in terms of efficiency) on GPUs. Memory accesses can be efficiently parallelized by decoding several codewords in parallel, as well as by using appropriate data structures. In this article we present the algorithms and data structures used to make log-domain decoding of the long LDPC codes specified by the DVB-T2 standard??at the high data rates required for television broadcasting??possible on a modern GPU. Furthermore, we also describe a similar decoder implemented on a general purpose CPU, and show that high performance LDPC decoders are also possible on modern multi-core CPUs.     

DVB-S2中LDPC码的阈值分析

DVB-S2的核心编码LDPC码采用不同的码率来适应不同的信道条件,阈值分析是信道条件和码率选择的关键,介绍了用EXIT曲线图法来进行阈值分析,该方法比密度进化法计算量大大减少,使得阈值分析变得更加简单,还介绍了可变码率信道编码在DVB中的应用.     

Early detection of successful decoding for dual-diagonal block-based LDPC codes

Low-density parity-check (LDPC) codes [1] have attracted much attention in the last decade owing to their capacityapproaching performance. LDPC codes with a dual-diagonal blockbased structure can be encoded in linear time with lower encoder hardware complexity [2]. This class of LDPC codes is adopted by a number of standards such as wireless LAN (IEEE 802.11n) [3], wireless MAN (IEEE 802.16e, WiMAX) [4] and satellite TV (DVB-S2) [5]. LDPC codes are commonly decoded by the iterative belief-propagation (BP) algorithm. The decoder checks the parity-check equations to detect successful decoding at the end of the iteration. The Tanner graph of an irregular LDPC code consists of nodes with different degrees such that coded bits have unequal error protection [6]. Coded bits associated with higher degree nodes tend to converge to the correct answer more quickly. Hence, in order to give better protection to the transmitted data, data bits are always mapped to higher degree nodes whereas parity bits are mapped to lower degree nodes in the encoding process. The commonly used parity-check equations Hc t ? 0t will be satisfied after all the coded bits are correctly decoded. However, as discussed above, data bits converge to the correct answer much more quickly than parity bits, so some unnecessary iterations are wasted waiting for the parity bits to be decoded. In this Letter, a new set of low-complexity check equations are derived for dual-diagonal block-based LDPC codes. Early detection of successfully decoded data can be achieved by exploiting the structure and degree of distribution of the dual-diagonal parity check matrix. The decoder power, speed and complexity can be improved by adopting these equations. Simulation shows that the coding gain performance is little changed.