RTD基高速多值量化器的设计

建立的RTD SPICE模型,与实际制作的GaAs基RTD器件进行了拟合验证.对四值量化器电路的工作原理进行了解释说明,通过器件参数的提取,对电路进行了模拟仿真,确定了电路相关参数.通过公式计算得出的电路阈值电压与模拟结果一致.最后对电路最大的工作频率进行了分析.     

2.5-10Gb/s光发射机驱动电路HEMT IC中器件模型参数

对高速调制器驱动电路HEMTIC中器件参数进行了研究,着重讨论了HEMT器件直流参数、交流参数对外调制驱动电路特性的影响,给出了满足电路性能要求的器件参数范围;对2.5-10Gb/sPHEMTIC光驱动电路进行了计算机仿真,眼图模拟结果表明满足2.5-10Gb/s高速光纤通信系统需要.     

2.5—10Gb/s光发射机驱动电路HEMT IC中器件模型参数

对高速调制器驱动电路 HEMT IC中器件参数进行了研究 ,着重讨论了 HEMT器件直流参数、交流参数对外调制驱动电路特性的影响 ,给出了满足电路性能要求的器件参数范围 ;对 2 .5— 10 Gb/ s PHEMT IC光驱动电路进行了计算机仿真 ,眼图模拟结果表明满足 2 .5— 10 Gb/ s高速光纤通信系统需要     

硅高压功率JFET开关性能

本文介绍一种垂直沟道结型场效应晶体管.给出器件的电参数、线性区等效电路、开关参数的测试电路及一些测试结果.对器件的开关参数进行了初步分析与计算.指出,器件的通态电阻R_(on)是涉及本器件开关性能的一个重要参数.最后,给出一例高速脉冲放大器的实际电路.     

SOI器件中瞬态浮体效应的模拟与分析

针对SOI器件中的瞬态浮体效应进行了一系列的数值模拟,通过改变器件参数,比较系统地考察了SOI器件中瞬态浮体效应,同时也研究和分析了瞬态浮体效应对CMOS/SOI电路(以环振电路为例)的影响,并提出了抑制器件浮体效应的器件结构和参数优化设计.     

HSpice在电路内部参数容差统计分析中的应用

提出一种基于HSpice的器件内部参数蒙特卡罗统计分析方法对电子电路进行仿真设计。针对PSpice软件只能采用特定库元件进行统计分析的局限性,研究HSpice蒙特卡罗分析的技巧、程序语句参数的设置、输出结果的判读等,解决基于高精度内部参数器件模型的电路性能仿真,给出应用该方法实现电路内部参数蒙特卡罗统计分析的仿真过程。可以有效地提高电路设计的准确性、可靠性和电子产品生产的合格率。实验表明这种方法可以对组成电路器件的任意参数进行蒙特卡罗统计分析,包括MOS管、运放等的模型内部参数,在优化电路设计中具有很高的实用性。     

基于遗传算法的开关电流存储电路的设计

针对开关电流存储电路存在固有误差和电路器件参数需要大量手工迭代计算等难题,提出基于遗传算法的开关电流存储电路设计方法.其主要思想是以Class AB栅极接地存储电路为基础,对其进行小信号模型分析,借助遗传算法对电路的电荷注入误差和时间响应性能进行多目标优化,获取电路中器件参数的最优Pareto解.采用0.5μm CMOS工艺参数,对电路进行PSPICE仿真测试.结果表明,优化设计的电路具有存储精度高、响应速度快等优点.     

SOI器件中瞬态浮体效应的模拟与分析

针对 SOI器件中的瞬态浮体效应进行了一系列的数值模拟 ,通过改变器件参数 ,比较系统地考察了 SOI器件中瞬态浮体效应 ,同时也研究和分析了瞬态浮体效应对 CMOS/SOI电路 (以环振电路为例 )的影响 ,并提出了抑制器件浮体效应的器件结构和参数优化设计 .     

共振隧穿二极管基础电路的模拟与分析

简单介绍了RTD的器件特性和器件模型 ,用HSPICE模拟出RTD与电阻、MOS晶体管、RTD本身结合的电路特性。通过对不同电路参数I V特性的模拟和分析 ,为理解RTD器件机理和构造复杂电路提供了初步的基础     

基于MOSFET的H桥式直流电机控制电路的设计

本文介绍了H桥式直流电机控制电路的原理,对驱动电路和电流保护电路中主要器件的参数进行了分析和计算,并通过测试验证了电路设计和参数计算的正确性。     

Design optimization methodology for deep-submicrometer CMOS deviceat low-temperature operation

The design optimization for 0.3-μm channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3-μm CMOS device, by utilizing electron beam (EB) lithography· Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K     

Two-line neuristor with active element in series and in parallel†

A neuristor of a constant K two-line active circuit proposed by the authors was realised and the dependence of neuristor characteristics on the circuit parameters was obtained. It is known that the neuristor proposed as a micro-logic device has many advantages. However, no functional device which works as the neuristor has been completed. The proposed neuristor models have not been satisfactorily developed as a micro-electronic device because they cannot be integrated due to their structural difficulties, or even if the integration is realized, the relation between the structure and the neuristor characteristics was often obscure.

From the above point of view, a two-line circuit is proposed in this paper which is easily integrated because of its simple structure and is easy to explain theoretically. The neuristor is realized by a lumped-constant K active circuit to obtain the dependence of the neuristor characteristics on the circuit parameters. As a circuit, a series and a parallel type neuristor are used into which an S-shaped and an N-shaped negative resistive element are inserted, respectively.

First, by transmitting pulses the circuit shows that the neuristor characteristics are realized by the constant K circuit. Next the dependence of the neuristor characteristics on the circuit parameters is obtained as a function of the impedance of the circuit element, and finally, to explain theoretically the measured results, the circuit is analysed by Gauss-Seidels method which improves the conventional phase plane analysis.

As a result, it is demonstrated experimentally that the neuristor can be realized using the constant K two-line circuit. The relation between the neuristor characteristics and the circuit parameters is also obtained. Almost all the experimental results are proved theoretically. The difference of the neuristor characteristics between the S-shaped and the N-shaped negative resistance element is demonstrated. Thus now knowledge for the optimum circuit structure in order to realize the neuristor with new negative resistance elements is presented.     

基于单片机便携式颜色自适应识别电路的设计

为解决电致变色器件的颜色变化受外界环境颜色控制的问题,设计了一种基于单片机的便携式颜色自适应识别电路。与传统颜色识别电路相比较,该电路利用数字式的颜色传感器来获取外界环境颜色,产生的数字颜色信号易于单片机进行处理。在电路中,下位机部分主要负责获取电致变色器件变色参数及控制电致变色器件的颜色变化;而上位机部分主要负责把下位机获取的电致变色器件变色参数进行电压到颜色的曲线拟合,并通过蓝牙通信把拟合曲线参数传递给下位机。结果表明,该电路能自动根据环境颜色提供-4～4 V范围步进为0.1 V的电压来驱动电致变色器件的颜色显示,与传统的颜色识别电路设计相比,识别的精度和速度都得到了明显改善。     

结势垒控制肖特基整流管的优化设计

本文在分析结势垒控制肖特基整流管工作原理的基础上，详细讨论了器件特性与结构参数的关系；给出了器件优化设计的依据，建立了适用于ＳＰＩＣＥ电路分析程序的器件等效电路模型。     

RTD的器件模型和模拟——共振隧穿器件讲座(9)

阐述了电路模拟在设计和研制大规模集成过程中的必要性和重要意义,器件模型在电路模拟中的重要性以及器件模拟与器件模型的关系;在器件模拟通用软件形成过程的基础上重点讨论了RTD的器件模型、器件模拟和电路模拟软件SPICE三个课题;介绍了基于物理参数I-V方程RTD模型和高斯函数、指数函数RTD直流模型;利用ATLAS器件模拟通用软件对RTD进行了器件模拟,得到了势垒和势阱宽度、E区掺杂浓度等对RTDI-V特性的影响;以包含RTD电路的SPICE电路模拟中的文字逻辑门为例,通过电路模拟验证了其逻辑功能,对设计该电路起到指导和参考作用。     

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET

In this work, the effect of lateral straggle on independently driven underlap double gate MOSFET (IDUDGMOS) is presented based on analog and digital circuit performances. The lateral straggle in IDUDGMOS devices is due to process induced source/drain out diffusion and it varies the desired device characteristics. For the analysis of this variation on circuit performance of the device, an Amplitude Modulator (AM) circuit and a SRAM circuit is considered for analog and digital circuit application considerations respectively. For the analysis of the device in AM circuit the parameters studied are the bandwidth, the gain and the linearity, correspondingly for SRAM circuit the parameters studied are the Static Noise Margin (SNM) and the circuit delay. The analysis of the AM circuit designed using the IDUDGMOS suggested that the power loss and the bandwidth of the circuit degrade with increasing lateral straggle. For the SRAM circuit the analysis suggests that larger straggle lengths in the device results in reduced time delay but, the SNM is smaller as well.     

Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations

Circuit aging simulation is seen as a true enhancement to device and circuit simulation. To predict aging of circuit performance, tested models for device parameters are needed in which the change in device behavior as function of time, given the biasing and temperature condition of the device in the circuit, is correctly modeled. The time scale here is the lifetime of the product. A circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism. Device aging models that can be implemented in such a circuit simulator are presented here for nMOS and DMOS (double diffused MOS) based on measurements and empirical modeling.     

Generator for a custom statistical bipolar transistor model

An automated model generator (MG) has been developed for a rectangular bipolar device with arbitrary and nonsymmetrical separations of rectangular regions around the emitter perimeter. The MG provides a transistor equivalent circuit whose parameters are determined using a distributed network representing a three-dimensional transistor configuration. The network accounts for nonlinear device dependencies associated with horizontal layout and process technologies. The elements of the distributed network are simple units whose parameters ar derived from measurements or two-dimensional process and device simulations. The MG is versatile and offers several photolithography and processing technology options, with recessed oxide or oxide-nitride defined standard or polysilicon-type base. The resulting lumped-equivalent circuit is used, along with related models of other transistors or device types, for statistical analysis computations of various circuit configurations at different operating temperatures.     

Design and analysis of a control system for an optical delay-line circuit used as reconfigurable gain equalizer

The design and analysis of a control system for a coherent two-port lattice-form optical delay-line circuit used as reconfigurable gain equalizer is presented. The design of the control system, which is based on a real device model and a least-square optimization method, is described in detail. Analysis on a five-stage device for the 32 possible solutions of phase parameters showed that, for some filter characteristics, the variations in power dissipation can vary up to a factor of 2. Furthermore, the solution selection has influence on the optimization result and number of iterations needed. A sensitivity analysis of the phase parameters showed that the allowable error in the phase parameters should not exceed a standard deviation of /spl pi//500 in order to achieve a total maximal absolute accuracy error not greater than approximately 0.6 dB. A five-stage device has been fabricated using planar lightwave circuit technology that uses the thermooptic effect. Excellent agreement between simulations and measurements has been achieved.     

On-line extraction of model parameters of a long buried-channel MOSFET

A buried-channel depletion MOS transistor has an implanted neutral conducting channel between the source and drain due to which the device works in a variety of modes such as accumulation, accumulation-depletion, depletion, inversion-depletion, inversion, etc., and presents a more complex structure than an enhancement-mode device. For precise circuit simulation, accurate and on-line extraction of model parameters has assumed significant importance. It is found that representing the implanted buried channel by an equivalent box with average doping and junction depth gives a convenient trade-off between simplicity in modeling and accuracy in device characterization. The present work proposes a method of deriving the necessary model parameters through the measurement of a single device parameter, namely drain conductance under different operating conditions. The on-line measurements carried on a boron-implanted relatively long buried-channel MOSFET have been used to predict the best box for the profile and give other model parameters necessary for circuit simulation. It is shown that the method is most insensitive to measurement conditions compared to other techniques.