一种用于大功率D类功率放大器的快速启动LDO

D类放大器的输出级晶体管始终工作在开关模式,效率很高,在便携式电子领域得到广泛应用.采用CSMC 0.5 μm BCD工艺,设计了一款应用于大功率D类放大器的低压差线性稳压器,对其结构和工作原理进行分析,重点讨论了各个关键电路模块的设计,改善了电源抑制比和启动时间.LDO的PSRR为100 dB @ 1 kHz,启动时间18 μs,负载能力225 mA,工作电压范围5.5～18 V,最小压差0.5 V,温度系数54×10-6/℃.     

用于数字D类放大器的双边PWM调制模块

文中介绍了一种双边PWM调制的数字D类放大器调制模块,使用伪自然采样法消除谐波失真。该伪采样算法是将牛顿-拉夫森迭代法和多项式逼近法相结合而形成的。近年来,虽有较多关于前沿PWM调制（LEPWM）和后沿PWM调制（TEPWM）的数字D类放大器的文献,但基于双边PWM（DEPWM）调制的数字 D类放大器方面的文献较少。因此本文利用现有的噪声整形技术,基于牛顿-拉夫森迭代法的伪采样算法等实现了一种用于数字D类放大器的双边PWM调制模块,并使用FPGA搭建了一个24位立体声数字音频D类放大器调制系统。经测试,该调制系统THD＋N@6 kHz性能达到-80.5 dB。     

设计Sigma-Delta A/D调制器结构

介绍Sigma Delta调制的基本原理。重点根据不同调制器结构的特性和产品的总体性能要求设计合适的调制器结构,实现其具体的电路总体结构,分析该电路结构特性对电路模块设计的影响,给出电路模块的设计原则和指标。芯片已在中芯国际0.18μm工艺线上流片成功,工作频率6.144 MHz,动态范围90 dB,信噪比88 dB,功耗9.4 mW,总谐波失真0.024 8%。     

一款高效率、高保真的D类音频放大器设计

设计了一款高效率、高保真的片上集成D类音频放大器.基于具有噪声整形特性的连续时间∑-△调制(CT-SDM)技术,并且通过恰当的环路设计,实现环路自振荡,而无需额外的振荡器,简化了电路,节省了芯片面积.核心电路采用低噪声、大带宽的OTA以减小输出噪声.该音频放大器在0.6μmBCD工艺下实现,裸片面积仅为1.67×2.5mm2.在4Ω负载条件下测试,输出功率120W时效率高达96%;1kHz输入信号,60W输出功率时,THD+N低至0.005%.     

大功率低THD+N的D类音频功率放大器

为了减小D类放大器,尤其是大功率D类音频放大器的总谐波失真加噪声(THD+N),提出了二阶双反馈闭环结构,有效改善了失真、电源抑制和信噪比等主要性能;通过引入前馈结构,改善了输入信号动态范围.基于CSMC 0.5 μm BCD工艺,采用该结构实现的双声道2×10 W D类音频功率放大器采用全差分结构和全桥输出,THD+N低至0.05%,PSRR可达82 dB @1 kHz,效率高于90%.     

2.5W低噪声CMOSD类音频功放设计

提出了一种基于0.5μm5VCMOS工艺的低噪声PWM调制D类音频功率放大器。该放大器在5V电源电压下以全桥方式可以驱动4Ω负载输出2.5W功率;转换效率等于87%,信噪比达94dB(负载8Ω,输出功率1W);THD+N仅0.05%(负载4Ω,输出功率1W);PSRR为68dB(频率1kHz)。分析了整体电路结构及其线性化模型,并着重介绍了高性能前置斩波稳定运算放大器(开环增益117dB,等效输入噪声16μV.Hz-1/2),线性三角波振荡电路(斜率偏差仅±0.2%)和功率器件、驱动电路的设计。最后给出了D类放大器的测试结果。     

0.1～4 GHz达林顿-共射共基结构的增益模块

提出了一种新型电路拓扑结构的增益模块,该增益模块为达林顿-共射共基结构,对 其工作原理进行了分析。基于AWR Microwave Office软件的仿真结果表明：达林顿晶体管共 射放大电路具有较强的电流放大能力,能有效提高增益;共基放大电路能抑制电路密勒效应 ,改善电路高频响应。设计了增益模块的版图,用2 μm InGaP/GaAs HBT工艺成功流片 ,测试结果表明：在01～4 GHz频率范围内,该增益模块最大增益为25 dB,最小 增益大于13.5 dB,在900 MHz工作频率时,该增益模块的P1dB为20 d Bm。     

一种高线性度100 kHz带宽∑△调制器

设计了一个100 kHz信号带宽、80 dB SNDR、3.3 V电源电压的单环三阶∑△调制器.电路采用AB类运放,可在较低静态功耗下实现较高的压摆率.电路采用UMC 0.18μm CMOS工艺制作,版图面积为1.7 mm×1.3 mm.芯片测试结果显示:在12 MHz时钟频率、60倍过采样下,调制器可达到100 kHz信号带宽,75.7 dB SNDR和98 dB SFDR.     

一种带有Trimming电路的Gm-C带通滤波器的设计

针对红外接收芯片中带通滤波器的功能要求,在G_m-C二阶带通滤波器架构的基础上,设计了引入非平衡差分对的跨导运算放大器、驱动外部负载的缓冲器、修调电路以及外部中心频率调整电路。该G_m-C二阶带通滤波器的中心频率、通带增益、带宽均正交可调。电路采用0.25μm标准CMOS工艺设计,然后使用Hspice软件对整体电路进行了仿真验证。仿真结果显示:该带通滤波器的中心频率为36.3 kHz,带通增益为23.2 dB,带宽为5.8 kHz,品质因数为5.3。该电路结构简单、容易集成,可广泛应用于红外遥控接收系统中。     

高线性度低功耗的4阶开关电容低通滤波器

介绍了一种应用于传感器的高线性度低功耗全差分4阶贝塞尔开关电容滤波器.该滤波器的运算放大器为输出AB类运算放大器,通过AB类运算放大器以及开关电容共模反馈的设计,降低了功耗.在运算放大器中设计了线性跨导环,并通过对电路的拓扑结构进行优化,提高了滤波器的线性度.测试结果表明,在采样频率为1 MHz下,该滤波器的截止频率为10.05 kHz.在输入信号频率为1 kHz,输出信号的总谐波失真(THD)为-89 dB(摆幅为2 V),功耗为5.54 mW,达到了高线性度、低功耗的设计要求.     

一种0.18m单层多晶硅CMOS音频-调制器

设计了一种应用于18位高精度音频模数转换器(ADC)的三阶Σ-Δ调制器。调制器采用2-1级联结构,优化积分器的增益来提高调制器的动态范围。采用栅源自举技术设计输入信号采样开关,有效提高了采样电路的线性度。芯片采用中芯国际0.18μm混合信号CMOS工艺,在单层多晶硅条件的限制下,采用MIM电容,实现了高精度的Σ-Δ调制器电路。测试结果表明,在22.05kHz带宽内,信噪失真比(SNDR)和动态范围(DR)分别达到90dB和94dB。     

应用于ΣΔADC的多级抽取滤波器面积有效实现方法

本文介绍了一种用于音频过采样模数转换器的多级抽取滤波器的面积有效实现方法。抽取滤波器的抽取倍数为256,通带波纹小于0.005dB,阻带抑制达到100dB。通带范围为0-20kHz,输出为48kHz的16比特信号。通过采用含RAM和ROM的面积有效架构,以及对一个运算周期中有效的指令调度,该抽取滤波器在XilinxFPGA上综合后仅使用了不到300个LUT和不到160个Slice。不同于串行或部分串行架构中运算速率通常大于输入采样速率的情况,该实现方法可使得运算速率和采样速率一致,从而简化整体ΣΔADC设计并降低功耗。架构中RAM和ROM的采用使得该抽取滤波器可编程,进一步可改进用于自适应滤波应用。最后,在Modelsim中的RTL仿真结果通过Matlab\Simulink程序进行了验证。     

A CMOS delta-sigma true RMS converter

Conventionally, monolithic electronics true rms converters are constructed by bipolar circuitry. This paper describes a new architecture based on delta-sigma (ΔΣ) modulation to realize a low-cost rms converter in CMOS technologies, especially intended for handheld digital multimeters. The signal-to-quantization noise ratio as well as transfer characteristics of this architecture have been deduced to obtain initial design parameters. The use of an indirect charge transfer technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy. Measured results show that this converter achieves a signal-to-noise ratio of 88 dB and a relative error of ±0.2% for arbitrary inputs with a signal crest factor up to three. The signal bandwidth exceeds 50 kHz, and the full-scale input range is greater than 0.4 V_rms. Without trimming and calibration, this converter has an absolute gain error less than ±0.4%. This chip is fabricated in a 0.8-μm double-poly, double-metal CMOS process and occupies active area of 1 mm ²     

三阶级联Sigma-Delta调制器设计

介绍2-1级联的三阶调制器设计结构，讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响：运用SIMULINK对调制器建模并仿真，模型中考虑．开关电容积分器的非理想因素对整个调制器的影响．并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2．50MHz时．该模型结构得到93dB的信噪失真比，可应用于实际的电路系统。     

84dB动态范围13b/400kHz/3V/5.88mW∑△模数转换器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现.电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm.调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW.测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB.     

A low-distortion BiCMOS seventh-order Bessel filter operating at2.5 V supply

This paper presents the design of a seventh-order continuous-time Bessel filter using a new low-voltage and highly linear BiCMOS transconductor. A high-gain and parasitic-insensitive integrator is obtained by using an active capacitor scheme. The filter has been designed to operate at a 2.5 V supply with a nominal -3 dB cutoff frequency of 600 kHz. It has been fabricated in 1 μm, double-poly 6-GHz BiCMOS process. The inband group delay variation is less than 10 ns. The total harmonic distortion (THD) measured with a 100 kHz input signal is less than -49 dB for a 2 V_pp amplitude and the dynamic range is 77 dB. The filter can be frequency tuned over almost one decade with a gain variation less than 0.2 dB in the passband. A common-mode rejection ratio (CMRR) of 53 dB in the passband is observed, thanks to a careful common-mode control strategy     

An adaptive PLL tuning system architecture combining high spectralpurity and fast settling time

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB     

A Co‐design Study of Filters and Oscillator for Low Phase Noise and High Harmonic Rejection

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co‐design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co‐design achieves a phase noise of ?130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co‐design of ?101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.     

Low-distortion bandpass /spl Sigma/-/spl Delta/ modulator for wireless radio receivers

A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.     

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.