实时OFDM-PON系统帧同步的设计与实现

利用Xilinx公司的现场可编程门阵列(FPGA)实现了一种简单的OFDM-PON实时系统帧同步算法。通过对帧同步模块的功能仿真验证和硬件资源消耗的分析,该算法具有准确性高、易实现和资源消耗少等优点。在OFDM-PON点对点实时系统中运用了该同步算法,在25km标准单模光纤上能够实时传输3.5Gb/s 64-QAM编码的光OFDM信号,误码率可以达到1.0×10-6。     

H.264指数哥伦布码解码部件的硬件设计和实现

提出了一种针对H.264视频编码标准的变长码-指数哥伦布码解码的硬件设计结构,对传统的桶形移位器进行优化,主要采用基于PLA的并行解码算法以达到实时解码,同时辅助使用串行解码算法降低硬件资源消耗,保证在能够对符合H.264标准baseline Profile的码流实时解码的基础上优化了电路资源,给出实现该硬件结构对应的FPGA仿真结果及其ASIC硬件规模.     

色域扩展中的快速查找表结构

在立方体插值算法的基础上,提出了一种适合于实时应用的快速查找表结构.其中将涉及颜色空间转换和色域扩展的复杂算法使用硬件上的综合查找表完成,使用了计算速度较快的四面体插值算法.同传统的立方体插值算法相比,有效降低了硬件资源消耗并提高了运算速度.     

基于FPGA的实时载波频率检测电路设计

为了实现窄带调制信号载波频率的快速准确获取并减少硬件资源消耗,基于FPGA设计一种综合哥兹柔(Goertzel)算法和能量重心估计算法的实时载波频率检测电路。首先,确定频率检测算法实现流程,在Matlab中进行了频谱和能量重心的仿真;接着提出一种低复杂度频率检测系统的硬件实现架构,以8个哥兹柔电路并行运行获取信号频谱,通过查找峰值谱线位置初步估计出信号频率;最后,采用能量重心估计法,精确估计出载波信号的频率。实验结果表明,设计的低复杂度实时频率检测硬件电路在资源消耗上仅为传统FFT方法的1 3,测频相对误差小于0.2%,2 048点频谱获取时间仅为103μs,易于硬件实现,可用于实时准确获取载波频率。     

面向实时数字信号系统关键链路延时的NoC映射方法研究

该文在面向功耗优化的经典NoC设计平台和映射算法基础上,针对实时数字信号处理电路固有的实时性特征,提出了一种新的面向最小化系统关键链路延时的NoC自主映射模型MM-Map。该模型在满足处理单元处理容限和链路带宽的约束下,采用基本遗传算法完成延时目标的优化求解。实验结果表明,该模型能节约一定硬件资源的消耗,得到近似全局最优延时解,映射过程简单,收敛效果好。     

基于折叠变换的CORDIC算法实现

在现代数字信号处理领域中,CORDIC算法是一种重要的数学计算方法。该算法采用一种迭代的方式,运算简便,被广泛应用于乘除法、开方以及一些三角函数运算当中。但CORDIC算法需要较高的迭代级数以保证运算精度,在进行FPGA实现时仍然会消耗较多的硬件逻辑资源。为进一步减少CORDIC算法实现时的资源消耗,设计并实现了一种基于折叠变换的CORDIC算法。相比传统的流水结构CORDIC算法,该折叠结构的CORDIC算法消耗的硬件资源大大减少。文中给出了这一方法的实现结构,并给出了仿真结果。     

WFQ权重比较电路的设计

讨论了一种基于前导零的WFQ权重比较电路的设计,主要描述了逻辑电路的设计方法、仿真和综合等.和传统的设计方法相比,基于前导零方法的设计不仅具有速度的优势,而且在电路的硬件资源消耗方面也具有较好的表现.     

一种减少频率槽的同步码捕获方法

针对大动态下同步码实时捕获中频率槽过多、硬件资源消耗大的问题，提出了一种减少频率槽数量的同步码捕获方法。新方法将频率槽数量减小一半后，利用频率槽中的同步码相关值进行多普勒的估计和多普勒补偿，将补偿后的数据进行同步码捕获。理论分析和仿真验证表明，新算法在完成相同的同步码捕获性能下，基本将硬件资源降低到了原有系统的一半。     

一种连续电子变倍算法的SOPC实现架构

基于双线性插值算法提出一种连续电子变倍的SOPC实现架构。该方法充分利用FPGA和NIOS软核各自优势,以单FPGA的SOPC实时实现了无级连续电子变倍功能,在减小设计难度的同时大大降低了对硬件资源的占用。实验结果表明,本文架构具备较好的电子变倍效果,可提高观察者对图像中小目标的分辨能力,在成像系统中具有较好的应用价值。     

基于改进cordic算法的NCO设计

提出了一种改进cordic(coordinate rotation digital compute,坐标数字旋转)算法,用于实现NCO(数控振荡器)的设计。该算法能够预先确定所有迭代的旋转方向,相对于传统cordic算法,减少了硬件资源消耗。采用Altra公司CycloneII系列芯片EP2C5AF256A7进行FPGA验证,结果符合设计要求。     

多尺度Harris角点检测的FPGA实现

针对实时图像处理的要求,提出了一种利用FPGA实现多尺度Harris角点提取的方法。通过简化高斯函数,实现了基于FPGA的尺度空间构建。分析了多尺度Harris角点检测算法,改进了响应值计算函数,通过改进算法步骤,在FPGA上并行搜索位置、尺度空间响应值的极大值,进一步提高了多尺度Harris角点检测的速度。硬件处理速度显示,设计适用于实时性要求高的图像处理领域。     

基于FPGA的三维视频系统实时深度估计

深度估计是基于视频加深度图像的三维视频系统中前端预处理的核心技术,其主要技术难题包括准确性、实时处理和大分辨率深度图获取等。本文提出一种实时深度估计的硬件实现方案,主要解决处理速度问题,并兼顾了准确性和大分辨率问题。本方案采用单片FPGA实现深度估计,其中采用census变换与SAD(Sum of Absolute Differences)混合的算法进行逐点匹配得到稠密深度图。硬件设计充分利用FPGA的大规模并行能力,并采用流水线设计提高数据通路的数据吞吐量,提升整个设计的时钟频率。实验表明,所提出的方案可实现全高清(1 920×1 080)分辨率视频实时深度估计。为了支持大分辨率图像并能观测距离相机较近的物体深度,本文方案视差搜索范围可以达到240pixels,帧率最高可达69.6fps,达到了实时和高清的处理目的。     

FPGA based multi-channel variable-length FFT implementation

High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform (FFT) application, such as Synthetic Aperture Radar(SAR) processing and medical imaging. In SAR processing, the image size could be 4 k×4 k in normal and it has become larger over the years. In the view of real-time, extensibility and reusable characteristics, an Field Programmable Gate Array(FPGA) based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper. The hardware implementation of FFT is partially reconfigurable architecture. Firstly, the proposed architecture in the paper has flexibility in terms of chip area, speed, resource utilization and power consumption. Secondly, the proposed architecture combines serial and parallel methods in its butterfly computations. Furthermore, on system-level issue, the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode. In case of sufficient FPGA resources, state processing of serial mode mentioned above is converted to pipeline mode. State processing of pipeline mode achieves high throughput.     

基于FPGA图像分块解码的系统设计

讨论了一种硬件实现卫星图像高速解码的系统设计方案。采用图像分块解码的方式,使用现场可编程门阵列（FPGA,Field Programmable Gate Array）的IP核实现片内缓存,减少了外挂RAM,降低了设计的复杂度。利用异步FIFO可以同时读写的特性,实现了码流检测与解码同时进行,并通过多路并行和流水线操作对图像码流进行高速解码。整个设计采用VHDL对算法完成建模和实现,仿真和综合结果表明该方案占用的硬件资源少,解码速度快,实现了图像码流解码的实时性和准确性,而且可移植性强,可以应用到图像处理的很多领域。     

Design of a real-time face detection architecture for heterogeneous systems-on-chips

Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a cascade classifier in real-time and resource-constrained systems. As case study, the proposed architecture has been tailored to accomplish the face detection task and integrated within a complete heterogeneous embedded system based on a Xilinx Zynq-7000 FPGA-based System-on-Chip. Experimental results show that, thanks to the proposed parallel processing scheme and the runtime adaptable strategy to slide sub-windows across the input image, the novel design achieves a frame rate up to 125fps for the QVGA resolution, thus significantly outperforming previous works. Such a performance is obtained by using less than 10% of on-chip available logic resources with a power consumption of 377  mW at the 100 MHz clock frequency.     

AVS编码器中帧内预测模块的硬件设计

根据AVS标准中帧内预测算法的特点,提出了一种应用于AVS高清实时编码器的帧内预测硬件设计方案.该设计中将亮度和色度预测共用一个预测单元,采用6路数据并行流水处理的结构,提高了处理速度.同时在分析AVS帧内预测各模式算法的基础上,结合移位寄存器操作实现各模式运算单元的进一步资源共享,简化了参考数据选择机制,减少资源消耗.实验结果表明,该设计完全能够满足高清视频图像(1 920×1 080,30 f/s(帧/秒))实时编码要求.     

Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model

A high performance digital architecture for the implementation of a nonlinear image enhancement technique is proposed in this paper. The image enhancement is based on an illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions. The algorithm shows robust performance with appropriate dynamic range compression, good contrast, accurate and consistent color rendition. The algorithm contains a large number of complex computations and thus it requires specialized hardware implementation for real-time applications. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Approximation techniques are used in the hardware algorithmic design to achieve high throughput. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 63 Mega-pixels (Mpixels) per second.     

Real-time image template matching based on systolic array processor

An architecture based on a systolic array for real-time image template matching is presented. The architecture consists mainly of four elements: a digitizer, a two-dimensional systolic array combined with variable-length shift register arrays, an adder tree, and a comparator. All the elements form a four-stage pipeline. The image data enter the pipe sequentially in the same order as the TV raster scan. The matching computation is, however, performed in a parallel manner. The analyses on time complexity and hardware complexity have shown that real-time performance is achieved. The analyses have also shown that the processing speed is higher and the hardware is simpler when compared to the architecture presented by Chou and Chen.     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

Block-level parallel processing for scaling evenly divisible images

Image scaling is a frequent operation in medical image processing. This paper presents how two-dimensional (2-D) image scaling can be accelerated with a new coarse-grained parallel processing method. The method is based on evenly divisible image sizes which is, in practice, the case with most medical images. In the proposed method, the image is divided into slices and all the slices are scaled in parallel. The complexity of the method is examined with two parallel architectures while considering memory consumption and data throughput. Several scaling functions can be handled with these generic architectures including linear, cubic B-spline, cubic, Lagrange, Gaussian, and sinc interpolations. Parallelism can be adjusted independent of the complexity of the computational units. The most promising architecture is implemented as a simulation model and the hardware resources as well as the performance are evaluated. All the significant resources are shown to be linearly proportional to the parallelization factor. With contemporary programmable logic, real-time scaling is achievable with large resolution 2-D images and a good quality interpolation. The proposed block-level scaling is also shown to increase software scaling performance over four times.