Efficient FPGA implementation of corrected reversible contrast mapping algorithm for video watermarking

This paper analyses and rectifies the shortcomings of reversible contrast mapping (RCM) algorithm for invisible watermarking. The proposed corrected RCM algorithm is tested by taking a gray scaled video input. The quality of services and structural similarity index matrix (SSIM) of each frame of the input video are tested in software environment. The video is obtained by OV7670 camera through Zed-board in fully field programmable gate array (FPGA) based hardware environment. FPGA devices based corrected high level synthesis of the proposed algorithm is presented. The suggested system engages pipeline structure and practices parallelism to achieve high performance. The quality of services and SSIM are also tested using FPGA devices and the comparative results with software implementations are explained. To process thirty (640 × 480) image blocks with 150 MHz clock we obtain a latency of 876.626 ns with throughput 62.328 Mbps. The critical path for single cycle is 5.992 ns. The number of resources essential is similar for watermark decoding with an improved schedule. The results acquired after implementation on Xilinx Virtex 7-XC7V2000T and programmable system-on-chip (Zynq - XC7Z030) FPGA devices confirm the practicability of real-time use with low cost and great speed.     

The secure wavelet transform

There has been an increasing concern for the security of multimedia transactions over real-time embedded systems. Partial and selective encryption schemes have been proposed in the research literature, but these schemes significantly increase the computation cost leading to tradeoffs in system latency, throughput, hardware requirements and power usage. In this paper, we propose a light-weight multimedia encryption strategy based on a modified discrete wavelet transform (DWT) which we refer to as the secure wavelet transform (SWT). The SWT provides joint multimedia encryption and compression by two modifications over the traditional DWT implementations: (a) parameterized construction of the DWT and (b) subband re-orientation for the wavelet decomposition. The SWT has rational coefficients which allow us to build a high throughput hardware implementation on fixed point arithmetic. We obtain a zero-overhead implementation on custom hardware. Furthermore, a Look-up table based reconfigurable implementation allows us to allocate the encryption key to the hardware at run-time. Direct implementation on Xilinx Virtex FPGA gave a clock frequency of 60 MHz while a reconfigurable multiplier based design gave a improved clock frequency of 114 MHz. The pipelined implementation of the SWT achieved a clock frequency of 240 MHz on a Xilinx Virtex-4 FPGA and met the timing constraint of 500 MHz on a standard cell realization using 45 nm CMOS technology.     

FPGA的双缓冲模式PCI Express总线设计

介绍了软件无线电平台中基于FPGA的双缓冲模式PCI Express（PCIE）总线的设计与实现。设计了基于Xilinx Virtex-6 FPGA的通用软件无线电平台,开发了基于Linux系统的驱动程序和PCIE硬核的DMA控制器。双缓;中提高了数据传输速度,节约了硬件资源。测试结果显示,该系统工作稳定可靠,读写速度...     

一种基于FPGA和PCI总线的天文图像实时采集与处理系统的设计

提出了一种基于FPGA和PCI总线的天文图像实时采集与处理系统设计;其包括硬件结构、FPGA数据获取和传输逻辑.该系统能够在FPGA中实现对最高峰值是660 MB/s,均值为200 MB/s,帧速率是2500 帧/s的高速CMOS相机天文图像数据的实时采集和处理,并由桥接芯片PCI9656通过PCI总线传输给PC机进行进一步处理.     

H.264/AVC中CAVLC编码器的硬件设计与实现

设计了一种H.264标准的CAVLC编码器,对原有软件流程进行部分改进,提出了并行处理各编码子模块的算法结构。重点对非零系数级(level)编码模块进行优化,采用并行处理和流水线相结合的结构,减少了cavlc编码的时钟周期,提供了稳定吞吐量。采用Xilinx公司VirtexⅡ系列的xc2v250 FPGA进行实现验证,最高时钟频率可达158.1 MHz,可满足实时编码H.264高清视频要求。     

TS201 LINK口光通信传输的接口设计

针对在应用中高速DSP TS201的LINK口不能直接通过光纤实现数据远程传输的缺陷,介绍了一种基于FPGA(Xilinx的Virtex-4系列中的XC4VFX60)的LINK口与光纤通信的接口设计。给出了DSPTS201的LINK口与光纤通信转换的硬件和FPGA逻辑设计实例,并对逻辑设计的时序进行了综合和仿真,最后在Virtual DSP开发环境中验证了接口设计的LINK口远程通信互连结果。结果表明通过接口设计电路的转换,TS201 LINK口实现了在物理层按照RocketIO方式通信,数据层按照LINK口协议通信的远程数据传输功能,数据传输速度单向为250 MB/s,双向为500 MB/s,且具有高速、可靠稳定等特点。     

Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation

In this paper, we propose evolvable reasoning hardware and its design methodology. In the proposed design methodology, case databases of each reasoning task are transformed into truth tables, which are evolved to extract rules behind the past cases through a genetic algorithm. Circuits for the evolvable reasoning hardware are synthesized from the evolved truth-tables. Parallelism in each task can be embedded directly in the circuits through the direct hardware implementation of the case databases. We developed the evolvable reasoning hardware prototype using Xilinx Virtex FPGA chips and applied it to the English-pronunciation-reasoning (EPR) task. The evolvable reasoning hardware for the EPR task was implemented with 270K gates, achieving an extremely high reasoning speed of less than 300 ns/phoneme. It also achieved a reasoning accuracy of 82.1% which is almost the same accuracy as NETTalk in neural networks and MBRTalk in parallel AI.     

FPGA implementation of image processing technique for blood samples characterization

This work presents a hardware implementation of an image processing algorithm for blood type determination. The image processing technique proposed in this paper uses the appearance of agglutination to determine blood type by detecting edges and contrast within the agglutinated sample. An FPGA implementation and parallel processing algorithms are used in conjugation with image processing techniques to make this system reliable for the characterization of large numbers of blood samples. The program was developed using Matlab software then transferred and implemented on a Vertex 6 FPGA from Xilinx employing ISE software. Hardware implementation of the proposed algorithm on FPGA demonstrates a power consumption of 770 mW from a 2.5 V power supply. Blood type characterization using our FPGA implementation requires only 6.6 s, while a desktop computer-based algorithm with Matlab implementation on a Pentium 4 processor with a 3 GHz clock takes 90 s. The presented device is faster, more portable, less expensive, and consumes less power than conventional instruments. The proposed hardware solution achieved accuracy of 99.5% when tested with over 500 different blood samples.     

VLSI architecture for low latency radix-4 CORDIC

The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques. In this paper, we propose a pipelined architecture using signed digit arithmetic for the VLSI efficient implementation of rotational radix-4 CORDIC algorithm, eliminating z path completely. A detailed comparison of the proposed architecture with the available radix-2 architectures shows the latency and hardware improvement. The proposed architecture achieves latency improvement over the previously proposed radix-4 architecture with a relatively small hardware overhead. The proposed architecture for 16-bit precision was implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesized for 16-bit precision with 90 nm CMOS technology library and the area-time measures are provided. This architecture was also implemented using Xilinx ISE9.1 software and a Virtex device.     

FPGA implementation of an enhanced chaotic-KASUMI block cipher

The radio link is a broadcast channel used to transmit data over mobile networks. Because of the sensitivity of this network part, a security mechanism is used to ensure users’ information. For example, the third generation of mobile network security is based on the KASUMI block cipher, which is standardized by the Third Generation Partnership Project (3GPP). This work proposes an optimized and enhanced implementation of the KASUMI block cipher based on a chaotic generator. The purpose is to develop an efficient ciphering algorithm with better performance and good security robustness while preserving the standardization. The proposed design was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technologies. The synthesis results and a comparison with previous works prove the performance improvement of the proposed cipher block in terms of throughput, used hardware logic resources, and resistance against most cryptanalysis attacks.     

一种AES算法的快速硬件实现

介绍了一种用FPGA来快速实现硬件IP核的AES算法的方法,采用Xilinx公司的Virtex XCV-1000-6器件,并给出了时序仿真图,结果表明了其有效性。     

An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41 Mbps for encryption and 37 Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.     

Rijndael加密算法在低成本FPGA上的实现

论文介绍了Rijndael加密算法的不同硬件实现方式。为了兼顾硬件资源和电路性能两个方面,根据XilinxFPGA内在的结构特点,设计采用了inner-round流水线结构,利用了FPGA的内置RAM和丰富的寄存器资源,在消耗很少资源的情况下获得了极高的加密速度。     

Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization

This paper presents Xilinx System Generator (XSG) model design for realization of reversible watermarking algorithm using Difference Expansion (DE) approach in System-On-Chip (SoC) Field Programmable Gate Array (FPGA) environment. The reversible watermarking is verified by taking a (4 × 4) sized test image and is applicable for larger sizes of cover images. The outcomes of the result demonstrate that the proposed structural design allows combining MATLAB-Simulink and XSG during graphical user interface for image processing applications. The superiority of the algorithm is justified by using comparative analysis with some well-known methods in both software and hardware environments. The method provides effectively higher PSNR at higher embedding capacity. It is also found that the method requires less time and hardware resources with throughput of 13.516 Mb/s at operational frequency of 80 MHz for real time implementation using FPGA.     

基于RISC-V的SM4算法扩展指令的设计与实现

为更好地在资源有限终端实现SM4密码算法,论文基于开源RISC-V指令集及VexRiscv处理器,设计实现SM4算法扩展指令集,包括两条SM4算法扩展指令分别对应SM4算法密钥扩展部分及密码算法部分,以低硬件资源开销换取基于软件实现SM4密码算法时更高的吞吐量.论文设计实现的SM4密码算法扩展指令,通过使用Xilinx...     

可重构的串行高级加密标准加解密电路设计

为了进一步提高高级加密标准(AES)算法在现场可编程门阵列(FPGA)上的硬件资源使用效率,提出一种可支持密钥长度128/192/256位串行AES加解密电路的实现方案。该设计采用复合域变换实现字节乘法求逆,同时实现列混合与逆列混合的资源共享以及三种AES算法密钥扩展共享。该电路在Xilinx Virtex-Ⅴ系列的FPGA上实现,硬件资源消耗为1871slice、4RAM。结果表明,在最高工作频率173.904MHz时,密钥长度128/192/256位AES加解密吞吐率分别可达2119/1780/1534Mb·s^(-1)。该设计吞吐率/硬件资源比值较高,且适用支持千兆以太网。     

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher’s method.     

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

The transmission rate in current passive optical networks can be increased by employing Orthogonal Frequency Division Multiplexing (OFDM) modulation. The computational kernel of this modulation is the fast Fourier transform (FFT) operator, which has to achieve a very high throughput in order to be used in optical networks. This paper presents the implementation in an FPGA device of a variable-length FFT that can be configured in run-time to compute different FFT lengths between 16 and 1024 points. The FFT reaches a throughput of 10 GS/s in a Virtex-7 485T-3 FPGA device and was used to implement a 20 Gb/s optical OFDM receiver.     

Virtex系列FPGA芯片的数据流结构

Virtex型FPGA芯片是Xilinx公司芯片系列中的一种,Virtex系列的数据流及配置逻辑与XC4000的数据流及配置逻辑有显著不同,但却与Xilinx的FPGA家族保持了很大的兼容性.这里详细介绍了Virtex系列FPGA芯片的数据流大小及结构.