栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

输出对CMOS反相器SEL特性的影响评估

文中通过计算机模拟的方法分析了器件在不同输出电平时,CMOS反相器单粒子闩锁（SEL）特性的变化。通过对器件输出电平不同时,不同衬底的CMOS反相器进行仿真研究,我们得出,P衬底器件输出为高电平时比输出为低电平时得到的闩锁电流大,而N衬底器件在输出不同时,得到的闩锁电流大小相近。对于同种衬底的器件在输出不同时对SEL的敏感性几乎相同。在深亚微米的器件中,输出对器件SEL特性的影响均较大,需要在研究器件SEL特性时把其考虑在内。     

An efficient CMOS line driver for 1.544-Mb/s T1 and 2.048-Mb/s E1 applications

A CMOS operational amplifier (OPAMP) for use as a line driver for high-speed T1/E1 data communication link is described. The differential output swing, using a single 3.3-V power supply, is 5.2-V peak-to-peak on a 20-/spl Omega/ load. Novel circuits are used to control the closed-loop output impedance, quiescent bias current, and frequency compensation to ensure stable operation over varying temperature and load conditions. A special circuitry tristates the output in case of power-supply failure. The OPAMP achieves a unity-gain bandwidth of 35 MHz with only 10 mA of quiescent current. A new output-current-sense circuitry is used to provide a current feedback to adjust the output impedance for proper line termination as well as to provide short-circuit protection from excessive output currents. Using 0.35-/spl mu/m n-well CMOS technology, the amplifier occupies 0.69 mm/sup 2/ of area.     

Design approach using tunnel diodes for lowering power in differential comparators

Adding two clocked tunnel diode pairs to the output ports of a differential amplifier enables high-speed current-mode switching at a lower tail current than in a transistor-only differential pair. The addition of the tunnel diodes also lowers the output open-circuit time constant of the differential pair leading to faster switching speed. As a design example, a return-to-zero D flip-flop is simulated for use as the decision circuit in a single-bit oversampling digital-to-analog converter. Indium phosphide-based heterojunction bipolar transistors and resonant tunneling diodes are used in the model simulation; both conventional and tunnel-diode-augmented circuits are compared. Power dissipation of 3.5 mW/latch at 100-GHz clock frequency with 60-dBc spur-free dynamic range (SFDR) is obtained in the tunnel diode/transistor flip-flop. In comparison with the transistor-only approach, power is reduced by approximately 1.6/spl times/ at the same speed and SFDR.     

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-V_T MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.     

A 3-V CMOS low-distortion class AB line driver suitable for HDSLapplications

A fully differential CMOS line driver for use in high bit-rate digital subscriber line (HDSL) services Is presented. The circuit is fabricated in a single-poly quad metal 0.35-μm process and achieves <-70-dB total harmonic distortion while driving up to ±2.4-V, 200-kHz signals into 30 Ω with a 3-V supply. The circuit features a closed loop gain of 6.0 with minimal input capacitance (<200 fF). The circuit requires less than 20 mA of quiescent current and is capable of delivering dynamic currents as large as 180 mA. The circuit is a multistage amplifier utilizing nested-Miller compensation and an enhanced class AB output stage     

A 1.544-Mb/s CMOS line driver for a 22.8-Ω load

A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 V_pp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm² using a 2-μm p-well CMOS technology     

低电压Charge-Recovery逻辑电路的设计

提出了一种新的适用于低电压工作的 sem i- adiabatic逻辑电路—— Dual- Swing Charge- Recovery L ogic(DSCRL) .该电路由 CMOS- latch- type电路及负载驱动电路构成 ,对负载的驱动为 full- adiabatic过程 .DSCRL 的电源为六相双峰值脉冲电源 ,低摆幅脉冲用于驱动负载 ,高摆幅脉冲用于驱动 CMOS- latch- type电路 .降低负载上摆幅时驱动负载的 NMOS管的栅压可以保持不变 ,有效地解决了传统的 adiabatic电路在低电压工作时 charge- re-covery效率降低的问题 .文中比较了 DSCRL 电路与部分文献中的 semi- adiabatic电路的功耗 ,DSCRL 在低电压工作方面     

基于40纳米CMOS工艺的500-MS/s 10-bit三通道电流舵型DAC的鲁棒性设计

A 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm 1P8M CMOS advanced technology is proposed.The central symmetry random walk scheme is applied for current source arrays to avoid mismatching effects in nano-CMOS design.The high-speed latch drivers can be self-adaptively connected to switches in different voltage domains.The experimental data shows that the maximum DNL and INL are 0.42 LSB and 0.58 LSB.The measured SFDR at 1.7 MHz output signal is 58.91 dB,58.53 dB and 56.98 dB for R/G/B channels,respectively.The DAC has good static and dynamic performance despite the single-ended output.The average rising time and falling time of three channels are 0.674 ns and 0.807 ns.The analog/digital power supply is 3.3 V/1.1 V.This triple-channel DAC occupies 0.5656 mm2.     

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.     

0.18μm CMOS 20Gb/s 1:2分接器设计

使用标准0.18μm CMOS工艺设计并实现了1:2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽,在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.     

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.     

A design for high-speed low-power CMOS fully parallelcontent-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-μm 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256×54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions     

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.     

An improved low offset latch comparator for high-speed ADCs

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.     

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

In this paper, we proposed a reliable ultra-low-voltage low-power latch design based on the probabilistic-based Markov random field (MRF) theory ,  and  to greatly improve the ability of noise-tolerance. Through MRF mapping decomposition, we map the previous state and the current state compatible logic function of the latch into the MRF network separately. In this way, we can overcome the challenge of applying Markov random field theory to sequential noise-tolerant circuits. In order to further lower the hardware cost and circuit complexity of the chip, we apply the absorption law and H-tree logic combination techniques [4] to simplify the circuit complexity of the MRF noise-tolerant latch circuit. To preserve the noise tolerant capability of MRF latch, we utilize the cross-coupled latching mechanism in the output of MRF latch. Finally, we apply the proposed MRF latch design in a 16-bit carry-lookahead adder circuit. In TSMC 90 nm CMOS process, our proposed circuit can operate reliably under a lower supply voltage of 0.55 V with superior noise tolerance and consumes only 31 μW power, which is 59.2% lower as compared with the conventional CMOS latch design.     

用于高速高精度流水线ADC的开关电容比较器

在65 nm CMOS工艺条件下,设计了一种用于高速高精度流水线ADC的开关电容比较器。采用单电容结构,实现了比较结果的最小化传输延迟。利用正反馈电容将采样网络的实极点调制为复极点,以减小采样传输延迟。用静态锁存器替代高速双尾动态锁存器,以适应正反馈的电容结构。数字驱动部分采用正反馈方式,以提升传输速度。Spectre仿真结果表明,在14位精度下,10 GHz带宽比较器的采样网络具有与20 GHz带宽MDAC的采样网络相同的传输延迟,从锁存器开始锁存到数字驱动输出的总传输延迟小于50 ps。