Co-synthesis and co-simulation of control-dominated embedded systems

This paper presents a methodology for hardware/software co-design with particular emphasis on the problems related to the concurrent simulation and synthesis of hardware and software parts of the overall system. The proposed approach aims at overcoming the problem of having two separate simulation environments by defining a VHDL-based modeling strategy for software execution, thus enabling the simulation of hardware and software modules within the same VHDL-based CAD framework. The proposed methodology is oriented towards the application field of control-dominated embedded systems implemented onto a single chip.     

Hardware/software co-design of the Stanford FLASH multiprocessor

Hardware/software co-design is a methodology for solving design problems in systems with processors or embedded controllers where the design requirements mandate a functionality and performance level for the system, independent of the hardware and software boundary. In addition to the challenges of functional correctness and total system performance, design time is often a critical factor. To design MAGIC, the programmable memory and communication controller for the Stanford FLASH multiprocessor, the authors employed a hardware/software co-design methodology. This methodology allowed them to concurrently design the hardware and software thereby reducing design time while simultaneously ensuring that the design would meet ambitious performance goals. Serializing the hardware and software design would have lengthened the design time and significantly increased the amount of redesign when the tradeoffs between the hardware and software implementations became clear late in the design process. The co-design approach led them to build a series of hierarchical simulators that allowed them to begin design verification early and to reduce the level of effort required to ensure a functional design     

新型智能存储SoC中NAND Flash控制器的软/硬件设计

介绍了新一代智能存储片上系统SSC,详细讨论了SSC中NAND Flash子系统的软/硬件设计;采用基于模板的划分方法,实现NAND读写控制器的软/硬件划分.SSC已生产并通过工业测试.结果表明,采用软/硬件划分的方法,NAND控制器的面积比纯硬件的实现方法减小58%,性能仅下降16%;比单纯ARM软件实现,速度平均提高20倍,同时具有软件的高灵活性.     

单片机创新实验板系统的设计与应用

传统教学用实验箱缺少培养学生独立设计硬件的环节,偏重软件设计,学生动手能力和创新性不足。为此,引入了模块化思想,将系统按功能分成6个模块,设计了创新实验板系统,采用串口通信原理,实现宿主计算机和单片机之间的通信问题。该系统要求学生根据需求,自主选材、独立设计并焊接实验板,编程之前需要自己设计实验方案并进行连线。该系统使学生参与从硬件设计到软件实现的单片机应用系统开发的全部过程,有效地弥补传统实验箱在硬件教学上的不足,全程培养学生动手能力和解决问题的能力。结果表明,本系统具有很好的稳定性和灵活性。     

Using method interception for hardware/software co-development

In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application. Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.     

Virtual Prototyping For Modular And Flexible Hardware-Software Systems

The goal of this work is to develop a methodology for fast prototyping of highly modular and flexible electronic systems including both, software and hardware. The main contribution of this work is the ability to handle a wide range of architectures. We assume that hardware/software partitioning is already made. This stage of the codesign process starts with a virtual prototype, an heterogeneous architecture composed of a set of distributed modules, represented in VHDL for hardware elements and in C for software elements, communicating through communication modules. This work concentrates on a modelling strategy that allow virtual prototype to be used for both cosynthesis (mapping hardware and software modules onto an architectural platform) and cosimulation (that is the joint simulation of hardware and software components) into an unified environment. The main contribution is the use of a multi-view library concept in order to hide specific hardware/software implementation details and communication schemes. In particular this approach addresses the problem of communication between the hardware and software modules.     

Software implemented fault tolerance: A methodology

A methodology for fault tolerance is proposed. This is based on the interactions between hardware and software in a scheme made of intelligent modules. This is particularly applicable to VLSI systems. Particular emphasis has been posed on the software implementation to reduce the external hardware, as this is the main source of hard core failures. A design of a duplex hybrid system with software implemented fault tolerance is presented to evidentiate the novel characteristics of this approach.     

Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors

While hardware/software partitioning has been shown to provide significant performance gains, most hardware/software partitioning approaches are limited to partitioning computational kernels utilizing integers or fixed point implementations. Software developers often initially develop an application using floating point representations built-in to most programming languages and later convert the application to a fixed point representation—a potentially time consuming process. In this paper, we present the Arizona Float ⇔ Fixed Hardware Library (AFFHL) consisting of efficient, configurable floating point to fixed point and fixed point to floating point hardware converters. By utilizing these converters, a system’s hardware/software implementation can be separated into a floating point domain consisting of the microprocessor and memory subsystem and a fixed point domain consisting of one or more partitioned hardware coprocessors. This separation enables a rapid hardware/software partitioning approach in which floating point software kernels can be implemented using fixed point hardware coprocessors without the need for application developers to first rewrite software applications as fixed point implementations. We further present an overview of a basic hardware/software partitioning methodology for rapidly partitioning computational kernels within floating point software application to either statically determined fixed point hardware coprocessors or dynamically adaptable fixed point hardware coprocessors in which the required fixed point representation can be dynamically determined and adjusted at runtime.     

基于SoC的DRM接收机ASIC设计

DRM是新一代的数字广播体制。针对DRM接收机的ASIC设计,提出了一种采用软硬件协同设计的SoC结构,给出了片上处理单元说明,SoC设计中的软硬件划分、协同设计和验证方法。最后给出了DRM接收机的性能。     

A software methodology for detecting hardware faults in VLIW data paths

The proposed methodology aims to achieve processor data paths for VLIW architectures able to autonomously detect transient and permanent hardware faults while executing their applications. The approach, carried out on the compiled application software, provides the introduction of additional instructions for controlling the correctness of the computation with respect to failures in one of the data path functional units. The advantage of a software approach to hardware fault detection is interesting because it allows one to apply it only to the critical applications executed on the VLIW architecture, thus not causing a delay in the execution of noncritical tasks. Furthermore, by exploiting the intrinsic redundancy of this class of architectures no hardware modification is required on the data path so that no processor customization is necessary.     

基于可配置VLIW结构DSP的RS译码算法设计

VLIW体系结构是高端DSP大多采用的体系结构,此结构有很强的指令级并行运算能力。一般的DSP应用开发,都是针对具体型号的DSP进行软件的设计和优化。为了更好地利用DSP资源、提高性能、节约成本,文中提出了一种软硬件协同设计的方法。通过Rs码的Euclid译码算法的实现,充分体现了可配置VLIW结构DSP的性能优势和开发周期短。达到面向应用的硬件和软件最优。     

VHDL-based rapid system prototyping

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.     

Design of telecommunication electronic systems using a hardware/software co-design methodology

Design of real-time electronic systems is critical since these systems include performance constraints as part of their requirements. The goal is to map all functions of such systems on to distributed hardware/software architecture in such a way that all performance constraints can be met. Hardware/software codesign approaches are an important issue. The aim of this paper is to discuss a case study of an X25 system design using a hardware/software co-design methodology. Several alternatives are discussed with respect to their performance. A prototype of the X25 system, which correctly implements the system functionality while meeting real-time requirements, has been experimentally checked.     

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores

We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modify the controller to interpret some of the instructions differently only within the initial test mode. In this paper, we have proposed a fuctional self-test methodology that is deterministic in nature. In our proposed architecture, a self test program called BIST Program is stored in an embedded ROM as a vehicle for applying tests. We first start with testing processor core using our proposed architedture. Once the testing of the processor core is completed, this core is used to test the embedded SRAMs. A test algorithm which utilizes a mixture of existing memory testing techniques and covers all important memory faults is presented in this paper. The proposed memory test algorithm covers 100% of the faults under the fault model plus a data retention test. The hardware overhead in the proposed architecture is shown to be negligible. This architecture is implemented on UTS-DSP (University of Tehran and Iran Communicaton Industries (SAMA)) IC which has been designed in VLSI Circuits and Systems Laboratory.     

基于SCA的软件无线电SoPC设计

软件通信体系架构为实现具有开放性、标准化、模块化的通用软件无线电平台提供了规范。为了实现无线通信系统的小型化,采用软硬件协同设计的方法构建了基于SCA的软件无线电SoPC系统,该系统实现了波形组件的动态配置和部署,以及硬件组件的部分重构。同时它具有效率高,体积小,功耗低,功能强的优点,具有很好的应用前景。     

软件化雷达技术研究

该文首先提出了软件化雷达(Software Radar)这一新技术概念, 并对软件化雷达的定义、定位、技术特点以及可能带来的影响进行了系统阐述。文中指出, 数字化雷达、软件化雷达和智能化雷达是现代雷达系统技术发展的3个不同阶段, 目前正处于从数字化雷达向软件化雷达过渡的重要时期。软件化雷达的核心特征体现在:标准化、模块化和数字化特征, 开放式的体系架构以及以软件技术为核心, 面向应用需求的开发模式。和传统的以硬件技术为核心, 面向专用功能的开发模式不同, 软件化雷达注重软件和硬件的解耦, 从而使得可以通过软件定义方式快速开发雷达系统, 并灵活地实现系统资源配置、功能扩展和性能提升, 以满足实际应用的需求。然后, 为了进一步阐述软件化雷达系统的技术特点, 该文对清华大学研制的软件化雷达信号处理系统RadarLab2.0进行了介绍。最后, 结合对空情报雷达的应用需求, 对软件化雷达技术的发展给出了建议。      

Synthesis of hardware models in C with pointers and complex datastructures

One of the greatest challenges in a C/C++-based design methodology is efficiently mapping C/C++ models into hardware. Many networking and multimedia applications implemented in hardware or mixed hardware/software systems now use complex data structures stored in multiple memories, so many C/C++ features that were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers for managing data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution, which fits current memory management methodologies, instantiates an application-specific hardware memory allocator coupled with a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. We present an implementation based on the SUIF framework along with case studies such as the realization of a video filter and an ATM segmentation engine     

Model‐based guidelines for user‐centric satellite control software development

Three persistent common problems in satellite ground control software are obsolescence, lack of desired features and flexibilities, and endless software bug fixing. The obsolescence problem occurs when computer and ground equipment hardware become obsolete, usually after only one‐third into the satellite mission lifetime. The software needs to be updated to accommodate changes on the hardware side, requiring significant work of satellite operators to test, verify, and validate these software updates. Trying to help solve these problems, we have proposed an object‐process methodology model and guidelines for developing satellite ground control software. The system makes use of a database‐driven application and concepts of object‐process orientation and modularity. In the new proposed framework, instead of coding each software function separately, the common base functions will be coded, and combining them in various ways will provide the different required functions. The formation and combination of these base functions will be governed by the main code, definitions, and database parameters. These design principles will make sure that the new software framework would provide satellite operators with the flexibility to create new features and enable software developer to find bugs quicker and fix them more effectively. Copyright © 2015 John Wiley & Sons, Ltd.