薄片半绝缘GaAs测试方法的研究

对在线工艺过程中实际使用的薄片（厚度为０．５ｍｍ左右）ＧａＡｓ试样中Ｃ浓度和ＥＬ２浓度的测量方法进行了研究，解决了常规方法难以测量薄片ＧａＡｓ中杂质含量的问题。     

薄片半绝缘GaAs测试方法的研究

对在线工艺过程中实际使用的薄片ＧａＡｓ试样中Ｃ浓度和ＥＬ２浓度的测量方法进行了研究，解决了常规方法难以测量薄片ＧａＡｓ中杂质含量的问题。     

Er,O离子共注入GaAs的二次离子质谱的研究

在Ⅲ－Ⅴ族半导体ＧａＡｓ外延层上共注入Ｅｒ和Ｏ离子（ＧａＡｓ：Ｅｒ，Ｏ）．经面对面优化退火后，光致发光（ｐｈｏｔｏｌｕｍｉｎｅｓｃｅｎｃｅ－ＰＬ）谱中观测到对应Ｅｒ３＋第一激发态到基态４Ｉ１３／２－４Ｉ１５／２跃迁，其相对强度较单注入Ｅｒ的ＧａＡｓ（ＧａＡｓ：Ｅｒ）增强１０倍，且谱线变窄．从二次离子质谱（ＳｅｃｏｎｄａｒｙＩｏｎＭａｓＳｐｅｃｔｒｏｍｅｔｒｙ－ＳＩＭＳ）和卢瑟福背散射实验给出退火前后Ｅｒ在ＧａＡｓ：Ｅｒ样品中的剖面分布．ＳＩＭＳ测量分别给出Ｏ注入前后Ｅｒ和Ｏ在ＧａＡｓ：Ｅｒ，Ｏ中的深度剖面分布，分析表明Ｅｒ和Ｏ共注入后形成光学激活有效的发光中心．     

通过温度控制LEC—GaAs单晶化学配比的实验研究

通过温度压力改变，使整个ＬＥＣ－ＧａＡｓ单晶生长过程Ａｓ损失最小。获得了化学配比较好的ＳＩ－ＧａＡｓ单晶。单昌表面离和，特别是单晶尾部结构缺陷也少。分析了ＬＥ－ＣＳＩ－ＧａＡｓ单晶生长过程Ａｓ的挥发和生长环境压力对生长的单昌位错密度的影响。     

热处理改善未掺杂LECGaAs中EL2分布均匀性的机理研究

本文以热处理方法研究了ＬＥＣＳＩ－ＧａＡｓ中ＥＬ２径向分分布变化规律，着重研究了不同的热处理后冷却方式对ＥＬ２分布均匀性改善程度的影响，讨论了ＬＥＣＧａＨｓ中ＥＬ２分布不均匀性的起源及热处理改善ＥＬ２分布均匀性的机理．     

非掺SI—GaAs单晶热处理的研究

采用闭管Ａｓ气氛保护高－低－中温热处理方法进行非掺ＳＩ－ＧａＡｓ单晶热处理的研究，结果表明晶体的科技司有明显的改善，一般晶体的迁移率可提高一倍以上，在Φ３英寸非掺ＳＩ－ＧａＡｓ单晶研究中，其晶体的电阻率不均匀性≤１５％，ＥＬ２ＲＳＤ≤５％，ＰＬ－Ｍａｐｐｉｎｇ≤９％。     

EL2能级对GaAs MESFET夹断电压的影响

在建立的理论模型基础之上,定量地分析了ＥＬ２能级对ＧａＡｓ ＭＥＳＦＥＴ夹断电压的影响,指出位于本征费米能级以下的ＥＬ２能级是影响ＧａＡｓ ＭＥＳＦＥＴ夹断电压大小的主要因素,ＥＬ２能级对ＧａＡｓ ＭＥＳＦＥＴ夹断电压的影响程度与ＥＬ２能给的缺陷密度呈线性关系。     

MBE生长InGaAs／GaAs应变层单量子阱激光器结构材料的研究

采用ＶａｒｉａｎＧｅｎⅡＭＢＥ生长系统研究了ＩｎＧａＡｓ／ＧａＡｓ应变层单量子阶（ＳＳＱＷ）激光器结构材料。通过ＭＢＥ生长实验，探索了Ｉｎ＿ｘＧａ＿（１－ｘ）ｔＡｓ／ＧａＡｓＳＳＱＷ激光器发射波长（λ）与Ｉｎ组分（ｘ）和阱宽（Ｌ＿ｚ）的关系，并与理论计算作了比较，两者符合得很好。还研究了材料生长参数对器件性能的影响，主要包括：Ⅴ／Ⅲ束流比，量子阱结构的生长温度Ｔ＿ｇ（ＱＷ），生长速率和掺杂浓度对激光器波长、阈值电流密度、微分量子效率和器件串联电阻的影响。以此为基础，通过优化器件结构和ＭＢＥ生长条件，获得了性能优异的Ｉｎ＿（０．２）Ｇａ＿（０．８）Ａｓ／ＧａＡｓ应变层单量子阱激光器：其次长为９６３ｎｍ，阈值电流密度为１３５Ａ／ｃｍ￣２，微分量子效率为３５．１％。     

非掺SI-GaAs单晶热处理的研究

采用闭管Ａｓ气氛保护高－低－中温热处理方法进行非掺ＳＩ－ＧａＡｓ单晶热处理的研究，结果表明晶体的特性有明显的改善，一般晶体的迁移率可提高一倍以上，在Φ３英寸非掺ＳＩ－ＧａＡｓ单晶研究中，其晶体的电阻率不均匀性≤１５％；ＥＬ２ＲＳＤ≤５％；ＰＬ－Ｍａｐ－ｐｉｎｇ≤９％。     

GaAs表面及AlxGa1—xAs／GaAsHBT外基区表面（NH4）2S／SiNx钝化工艺研究

分析了ＡｌｘＧａ１－ｘＡｓ／ＧａＡｓＨＢＴ外基区表面复合电流及外基区复面复合速度对直接增益的影响，用光致发光（ＰＬ）谱和Ａｌ／ＳｉＮｘ－Ｓ／ＧａＡｓＭＩＳ结构ＣＶ特性，研究了ＧａＡｓ表面（ＮＨ４）２Ｓ／ＳｉＮｘ钝化工艺的效果及其稳定性。结果表明，ＥＣＲ－ＣＶＤ淀积ＳｉＮｘ覆盖并在Ｎ２气氛中退火有助于改善ＧａＡｓ表面硫钝化效果的稳定性，在此基础上形成了一套包括（ＮＨ４）２Ｓ处理，ＳｉＮｘＥＣＲ－ＣＶ     

Preparation of silicon-on-gallium arsenide wafers for monolithicoptoelectronic integration

A process is described which combines silicon-on-insulator (SOI) and wafer bonding techniques to create thin (≈100 nm) single-crystal silicon layers on oxide coated gallium arsenide wafers for use in optoelectronic integration. Using a GaAs substrate for the integration eliminates the thermal expansion coefficient mismatch problems which have blocked monolithic integration of thick, stress sensitive optoelectronic devices on silicon, without compromising the performance of CMOS circuitry which can be fabricated in very thin, compressively strained silicon layers using SOT techniques     

Direct bonding of GaAs films on silicon circuits by epitaxial liftoff

Epitaxial liftoff has emerged as a viable technique to integrate GaAs with silicon. The technique relies on the separation of a thin epi-GaAs film from its substrate followed by direct bonding of the thin film to a silicon substrate. The silicon substrate has to meet certain planarity and smoothness conditions in order to obtain high quality bonding. Unfortunately, processed silicon IC chips do not satisfy these conditions. In this paper, we report on the results of two different planarization techniques, plasma etch back and chemical-mechanical polishing, to integrate GaAs LEDs with silicon circuits using epitaxial liftoff. 4 by 8 arrays of GaAs LEDs have been integrated with silicon driver circuits using plasma etch back. We also have lifted off areas as large as 500 mm² and bonded them on 5″ device wafers by chemical-mechanical polishing. This can be essential for mass production of optoelectronic devices based on epitaxial liftoff.     

Transfer of n-type GaSb onto GaAs substrate by hydrogen implantation and wafer bonding

Many GaSb devices would greatly benefit from the availability of a semi-insulating substrate. Since semi-insulating GaSb is not currently available, the formation of thin GaSb layers through wafer bonding and tranfer onto a semi-insulating GaAs substrate was investigated. GaSb-on-insulator structures, formed on GaAs substrates, were realized by the ion-cut process using H⁺ ions. Blistering, bonding and layer splitting phenomena were studied to optimize the ion dose and the process window. Bonded structures of thin layers of GaSb bonded to GaAs wafers were formed using a borosilicate glass (BSG) layer. The transferred GaSb layers were characterized by atomic force microscopy, MeV helium ion channeling and high-resolution x-ray diffractometry. The transferred film possessed a narrow x-ray linewidth of about 140 arcsec indicating improved crystalline quality over the direct growth of GaSb on GaAs.     

GaAs on Si-the ultimate wafer?

There are two basic reasons why growing GaAs on Si could be worthwhile. First, it could provide a low-cost, robust source of GaAs wafers. Growing single crystals of GaAs is relatively difficult, and GaAs wafers are generally smaller and more expensive than their silicon counterparts. They are also more fragile and prone to breakage. Secondly, it would allow high-speed digital Si, high-frequency analogue GaAs and the interchip connections to be integrated on a single substrate. The author discusses the defect densities of the GaAs layer due to lattice mismatch and then describes how the problem can be overcome by using strained layer superlattices grown by MOVPE     

Wafer bonding for III–V on insulator structures

The InP and GaAs wafers were bonded to GaAs substrates using a siliconnitride intermediate layer. Key process parameters include the silicon-nitride surface roughness and density as determined by atomic-force microscopy and x-ray reflectivity. We demonstrate that silicon nitride can be bonded without any chemical-mechanical polishing step. Silicon-nitride films produced by plasma-enhanced chemical-vapor deposition (PECVD) and deposition by sputtering were compared for bonding compatibility. Smooth silicon-nitride layers (root-mean-square roughness <0.7 nm) were found to produce large areas of bonded material and an oxygen-plasma treatment (200 mtorr, 200 W, 60 s) produced strong nitride/nitride bonding. The strain in the InP layer after transfer to the GaAs substrate was determined using x-ray reciprocal-space mapping (RSM). The crystalline quality of the InP layer was examined with high-resolution x-ray scattering.     

热处理中As压对半绝缘GaAs缺陷的影响

在 95 0°C和 1 1 2 0°C温度下 ,对非掺杂半绝缘 LECGa As进行了不同 As气压条件下的热处理 ,热处理的时间为 2～ 1 4小时。发现不同 As压条件下的热处理可以改变 Ga As晶片的化学配比 ,并导致本征缺陷和电参数的相应变化。在 95 0°C和低 As气压条件下进行 1 4小时热处理 ,可在样品体内 (表面 1 5 0 μm以下 )引入一种本征受主缺陷 ,使电阻率较热处理前增加约 5 0 % ,霍尔迁移率下降 70 %。这种本征受主缺陷的产生是由于热处理过程中样品内发生了 As间隙原子的外扩散。提高热处理过程中的 As气压可以抑制这种本征受主缺陷的产生。真空条件下在 1 1 2 0°C热处理 2～ 8小时并快速冷却后 ,样品中的主要施主缺陷 EL2浓度约下降一个数量级 ,提高热处理过程中的 As气压可以抑制 EL2浓度下降。这种抑制作用是由于在高温、高 As气压条件下 ,发生了间隙原子向样品内部的扩散     

Formation of graphite/sic structures by the thermal decomposition of silicon carbide

The conditions in which carbon layers are synthesized on the surface of silicon carbide (SiC) wafers by thermal decomposition are studied. The effect of temperature and composition of the gas atmosphere on the structural properties of the layers being synthesized is analyzed. The conditions in which continuous graphite films with both single-crystal and polycrystalline structure can be obtained are determined.     

Characterization of polycrystalline silicon wafers for solar cells sliced with novel fixed‐abrasive wire

For slicing crystalline silicon ingots, we have developed a novel fixed‐abrasive wire where diamond grit is fixed onto a bare wire by resin bonding. The properties of the wafers sliced using a multi‐wire saw with the fixed‐abrasive wire have been investigated. When compared with the wafers sliced with the loose‐abrasive wire, the slicing speed is improved by approximately 2.5‐fold and the thicknesses of saw‐damage layers are reduced by more than a factor of two. Polycrystalline silicon solar cells have been fabricated for the first time utilizing the wafers sliced with the fixed‐abrasive wire, and the cells with the saw‐damage etching depth of 7 µm have shown photovoltaic properties comparable to those prepared using the wafers sliced with the loose‐abrasive wire and subsequently etched to remove the damage layers up to 15 µm. It has been clarified that wafer slicing using the fixed‐abrasive wire is promising as a next‐generation slicing technique for fabrication of solar cells, particularly thin silicon cells where the wafer thicknesses approach or become less than 150 µm. Copyright © 2010 John Wiley & Sons, Ltd.     

GaAlAs／GaAs发光管中深能级与暗缺陷关系

本文用DLTS和瞬态单电容技术研究了液相外延生长的GaAlAs/GaAs有源层掺Si器件的深能级，用红外显微镜测量了近场EL图像，研究了深能级及暗结构缺陷的器件的影响及它们间的关系。     

基于硅氧化层的嵌入式传输线制造

在有损耗的硅衬底上试制了传输线(微带以及共面波导),并嵌入在CMOS Cu/SiO2互连层中.对传输线的几何尺寸与其特征阻抗、损耗以及衰减因子进行了研究.结果表明嵌入在硅氧化层中的微带和共面波导可以在有损耗的硅片上低损耗地实现,为在硅片上设计微波和毫米波电路提供了必要的无源器件.