Characterization of the novel polysilicon TFT with a subgatecoupling structure

Proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

Thick-layered etched-contact amorphous silicon transistors

We introduce a new thick-layered, etched-contact a-Si:H TFT (TLEC-TFT) structure which allows the use of thick a-Si:H layers without increasing the TFT contact resistance. This device facilitates the integration of high-performance TFTs and thick-layered photo-transistors in a-Si:H-based image sensors. The TLEC-TFT is fully compatible with the conventional TFT fabrication process and requires no extra masking steps. For low values of the drain-to-source voltage, our new TFT boosts the linear region current by two orders of magnitude over that of conventional TFTs with identically thick a-Si:H layers. By removing the adverse effects of contact resistance in transistors with thick a-Si:H layers, our TLEC-TFT design allows us to compare the performance of TFTs with thick and thin a-Si:H layers. We find that the width of the conduction-band tail decreases in thick-layered a-Si:H TFTs. This reduction in the width of the band tails results in an increase in the TFT mobility and subthreshold slope. Consequently, thick-layered, etched-contact TFTs possess higher overall current-drive capabilities compared to conventional, thin-layered TFTs. We present experimental evidence which correlates the width of the conduction-band tail to the density of as-deposited free carriers     

Characteristics of offset-structure polycrystalline-siliconthin-film transistors

In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n^- region between channel and n⁺ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5×10¹³ cm^-2 phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

Mirrored OLED pixel circuit for threshold voltage and mobility compensation with IGZO TFTs

In this paper, pixel circuit using mirroring structure with Indium–Gallium–Zinc oxide (IGZO) thin film transistors (TFTs) for active matrix organic light emitting diode (AMOLED) display is proposed. This pixel circuit consists of only four TFTs, and one capacitor. Due to the mirroring structure, characteristic of the driving TFT can be precisely sensed by the sensing TFT, which is deployed in a discharging path for gate electrode of the driving TFT. This discharging process is strongly dependent on threshold voltage (V_T) and effective mobility of the sensing TFT. Circuit operating details are discussed, and compensation effects for threshold voltage shift and mobility variations are verified through numerical derivation and SPICE simulations. Furthermore, compared with conventional schematics, the proposed pixel circuit might have much simplified external driving circuits, and it is a promising alternative solution of high performance AMOLED display.     

Halo LDD结构多晶硅薄膜晶体管的模拟研究

提出了多晶硅薄膜晶体管的一种Halo LDD新结构,这种结构是在基于LDD结构的基础上,在沟道靠近源、漏端引入高掺杂的Halo区.并利用工艺和器件模拟软件对该Halo LDD P-Si TFT的电学特性进行了分析,并将其与常规结构、LDD结构和Halo结构进行了比较.发现Halo LDD结构的P-si TFT能有效地降低泄漏电流、抑制阈值电压漂移和Kink效应;减少因尺寸减小后所带来的一系列问题.     

A novel self-aligned offset-gated polysilicon TFT using high-/spl kappa/ dielectric spacers

In this letter, a novel self-aligned offset-gated Poly-Si thin-film transistor (TFT) using high-/spl kappa/ dielectric Hafnium oxide (HfO/sub 2/) spacers is proposed and demonstrated. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. The permittivity of the deposited HfO/sub 2/ is approximately 20. Experimental results show that with the high vertical field induced underneath the high-/spl kappa/ spacers, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, compared to the conventional lightly doped drain or oxide spacer TFTs. The on-state current in the offset-gated Poly-Si TFT using the HfO/sub 2/ spacers is approximately two times higher than that of the conventional oxide spacer TFT.     

Novel Offset-Gated Bottom Gate Poly-Si TFTs With a Combination Structure of Ultrathin Channel and Raised Source/Drain

We propose an offset-gated bottom gate polycrystalline silicon thin-film transistor (TFT), with a combination structure of ultrathin channel and raised source/drain, employing a simple process of the back surface exposure. It is experimentally and simulatively demonstrated that the new device has lower leakage current and better saturation characteristics, as compared with the conventional non offset TFT, due to the lateral electric field near the drain, which is reduced by the proposed structure. Moreover, the proposed TFT exhibits much better ON/OFF current ratio because the high current drive due to the raised source/drain structure is enough to compensate for the ON-state current reduction due to the offset-gate structure.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

Highly Robust Bendable Oxide Thin‐Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers

Advancement in thin‐film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a‐IGZO semiconductor layer. The robustness of the a‐IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays.     

高性能钆铝锌氧薄膜晶体管的制备

本文研究并制备了钆铝锌氧薄膜和以钆铝锌氧为有源层的薄膜晶体管。钆铝锌氧薄膜材料的光致发光光谱和透过率说明钆铝锌氧薄膜在透明显示方向的应用潜力。透射电子显微镜揭示了钆铝锌氧薄膜的非晶态微观结构。钆铝锌氧薄膜晶体管显示了良好的转移特性和输出特性。器件开关比大于10~5、饱和迁移率约为10cm~2·V~(-1)·s~(-1)。实验结果表明,钆铝锌氧薄膜可用作氧化物薄膜晶体管的有源层材料;钆铝锌氧薄膜晶体管可作为像素电路的驱动器件。     

Characteristics of high-K spacer offset-gated polysilicon TFTs

In this paper, a self-aligned offset-gated poly-Si TFT using high-K dielectric (Hafnium oxide, HfO/sub 2/) spacers for channel scaled-down system-on-panel applications is experimentally demonstrated for the first time. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. Numerical simulations show that with the high vertical field induced underneath the high-K spacer, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, comparing to the conventional lightly doped drain or oxide spacer TFTs. The experimental on-state current in the HfO/sub 2/ spacer offset-gated poly-Si TFT is approximately two times higher than that of the conventional oxide spacer TFT with the same leakage current.     

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V and it is robust and promising for high-resolution display.     

A novel high-performance poly-silicon thin film transistor with aself-aligned thicker sub-gate oxide near the drain/source regions

Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9×10⁶ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V_GS=-15 V and V_DS=10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.     

A new current scaling pixel circuit for AMOLED

A new active-matrix organic light-emitting diode (AMOLED) pixel design, composed of four polycrystalline silicon thin-film transistor (poly-Si TFT) and one capacitor, is proposed by employing a novel current scaling scheme. The simulation results, based on the measured characteristics of an OLED and poly-Si TFTs, show that the proposed pixel design would scale down the data current more effectively, so as to guarantee a lower charging time compared with the conventional current mirror structure, as well as successfully compensate the variation of the electrical characteristics of the poly-Si TFTs, such as the threshold voltage and mobility.     

A high-performance multichannel dual-gate poly-Si TFT fabricated by excimer laser irradiation on a floating a-Si thin film

A new excimer laser annealing (ELA) process that uses a floating amorphous-Silicon (a-Si) thin film with a multichannel structure is proposed for high-performance poly-Si thin-film transistors (TFTs). The proposed ELA method produces two-dimensional (2-D) grain growth, which can result in a high-quality grain structure. The dual-gate structure was employed to eliminate the grain boundaries perpendicular to the current flow in the channel. A multichannel structure was adapted in order to arrange the grain boundary to be parallel to the current flow. The proposed poly-Si TFT exhibits high-performance electrical characteristics, which are a high mobility of 504 cm/sup 2//Vsec and a low subthreshold slope of 0.337 V/dec.     

A high-voltage polysilicon TFT with multigate structures

An approach is proposed for obtaining a high-voltage thin-film transistor (TFT) with multigate structure where polysilicon TFTs are connected in series. A basic principle for high-voltage operation has been investigated in detail through calculations based on a model describing log I_DS-V_GS characteristics observed in a single-gate polysilicon TFT. It has been found that off-state (V_GS<0) operation of the polysilicon TFT causes a large increase of breakdown voltage of the multigate TFT with the result that a nearly equal fraction of drain voltage is applied across the region around each elemental TFT. The breakdown voltage of drain of the fabricated multigate TFT which has five elemental TFTs has been elevated up to 80 V