Polysilicon gate enhancement of the random dopant induced thresholdvoltage fluctuations in sub-100 nm MOSFETs with ultrathin gateoxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3D) “atomistic” simulation technique. MOSFETs with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled to thickness in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect of the polysilicon grain boundaries on the threshold voltage variation are also presented     

A geometrical model of the threshold voltage of short and narrow channel MOSFETs

A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

The behavior of narrow-width SOI MOSFETs with MESA isolation

Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

Double jeopardy in the nanoscale court [MOSFET modeling]

Physics-based compact short-channel models of threshold voltage and subthreshold swing for undoped symmetric double-gate MOSFETs are presented, developed from analytical solutions of the two-dimensional Poisson equations in the channel region. These models accurately characterize the subthreshold and near-threshold regions of operation by appropriately including essential phenomena such as volume inversion and the dominance of mobile charges over fixed charges under threshold conditions. Explicit, analytical expressions are derived for a scale length, which results from an evanescent-mode analysis. These equations readily quantify the impact of silicon film thickness and gate oxide thickness on the minimum channel length and device characteristics and can be used as an efficient guideline for device designs. These newly developed models are exploited to make a comprehensive projection on the scaling limits of undoped double-gate MOSFETs. On the individual device level, model predictions indicate that the minimum channel length can be scaled beyond 10 nm for a turn-off behavior of S=100 mV/dec for a silicon film thickness below 5 nm and an electrical equivalent oxide thickness below 1 nm.     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Threshold voltage model for deep-submicrometer MOSFETs

The threshold voltage, V_th, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V_th on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V_th dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined     

Modeling the anomalous threshold voltage behavior of submicrometerMOSFET's

A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration     

Analytical model for threshold voltage shift due to impuritypenetration through a thin gate oxide

We derived an analytical model for the threshold voltage shift due to impurity penetration through gate oxide and evaluated the thermal budget for pMOS devices with a thin gate oxide. The threshold voltage shift decreases as the channel doping concentration increases, but the decrease is quite small. The allowable surface concentration of the penetrated impurity increases as the gate oxide thickness decreases if the allowable threshold voltage shift is constant. Therefore, the allowable diffusion length normalized by the gate oxide thickness d_ox increases with decreasing d_ox     

全耗尽SOI LDMOS阈值电压的解析模型

通过准二维的方法,求出了全耗尽SOILDMOS晶体管沟道耗尽区电势分布的表达式,并建立了相应的阈值电压模型。将计算结果与二维半导体器件模拟软件MEDICI的模拟结果相比较,两者误差较小,证明了本模型的正确性。从模型中可以容易地分析阈值电压与沟道浓度、长度、SOI硅膜层厚度以及栅氧化层厚度的关系,并且发现ΔVth与背栅压的大小无关。     

A compact pre- and post-stress I-V model for submicrometerburied-channel pMOSFETs

In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

90nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性(英文)

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流。为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视。然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性。在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3nm的二氧化硅pMOSFET经过125℃和10.7MVcm的电场1h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差。在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16V,可以符合90nm工艺1V特操作电压的安全范围内。     

Short channel epi-MOSFET model

We show how threshold voltages and the electric field perpendicular to a channel are controlled by varying the thickness of the epi-layer in long epitaxial channel MOSFET devices (epi-MOSFETs). Using our proposal of a two-region polynomial potential distribution and a universal boundary condition that effectively expresses the variation of depletion width along a channel, we calculated the two-dimensional (2-D) potential distribution. We also derived a threshold voltage model for short channel epi-MOSFETs. Our model reproduces the numerical data of sub-0.1-/spl mu/m gate length devices, and predicts that the short channel immunity of these devices is not as good as predicted by the previous model. However, their performance is superior to that of double-gate SOI MOSFETs.     

动态阈值nMOSFET阈值电压随温度退化特性

对动态阈值nMOSFET阈值电压随温度退化特性进行了一阶近似推导和分析。动态阈值nMOSFET较之普通nMOSFET,降低了阈值电压温度特性对温度、沟道掺杂浓度及栅氧厚度等因素的敏感程度。讨论了动态阈值nMOSFET优秀阈值电压温度特性的内在机理。动态阈值nMOSFET优秀的阈值电压随温度退化特性使之非常适合工作于高温恶劣环境。     

90 nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2 nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流.为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视.然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性.在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5 nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3 nm的二氧化硅pMOSFET经过125℃和10.7MV/cm的电场1 h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差.在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16 V,可以符合90 nm工艺1 V特操作电压的安全范围内.     

Analytical threshold voltage model for short channeln+-p+ double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation in the channel region, we have developed models for short channel n⁺-p⁺ double-gate SOI MOSFETs, and showed how to design a device with a decreased gate length, suppressing short channel threshold voltage shift ΔVth and subthreshold swing (S-swing) degradation. According to our model, we can design a 0.05 μm L_G device of which threshold voltage is 0.2 V, ΔVth is 25 mV, and S-swing is 65 mV/decade with a 3-nm-thick gate oxide and 12-nm-thick SOI