多晶硅发射极晶体管直流特性研究

研究了砷注入多晶硅发射极晶体管的直流特性,并与采用常规平面工艺制作的晶体管性能进行了比较.结果表明多晶硅发射极晶体管具有较高的发射效率,高的电流能力,改善了EB击穿和CB击穿.电流增益依赖于淀积多晶硅前的表面处理条件.     

一种高速高压NPN管的研制

把Ｎｉｎｇ－Ｔａｎｇ测试发射极电阻的方法进行扩展，用来测试多晶发射极界面氧化层电阻，作发射极界面氧化层电阻与多晶硅发射极晶体管退火的优化实验，获得退火的优化工艺条件，并由此成功地研制出ＢＶＣＥＯ≥３０，ＢＶＣＢＯ＝７５Ｖ，ｆｒ＝２ＧＨｚ，β＝１８０的多晶硅发射极晶体管。用扩展电阻ＳＳＭ１５０型测多晶硅发射极晶体管的纵向杂质分布，得出多晶硅发射极晶体管的发射区结深为５０ｎｍ，基区结深为２０ｎｍ。     

亚微米双层多晶硅自对准双极晶体管性能研究

本文采用亚微米工艺和自对准技术制作了发射区宽度分别为0.8μm和0.4μm的两种双层多晶硅自对准双极晶体管。其中采用的是深沟和LOCOS两种隔离联合的隔离方法;EB间自对准是通过均匀的高质量的SiNx侧墙实现的,EB结击穿电压高达4.5V;窄的发射区使得发射极多晶硅在发射区窗口严重堆积,引起了双极晶体管的电流增益增大,同时也降低了管子的速度。工艺和器件模拟显示,发射极多晶硅采用原位掺杂技术,双极晶体管的性能得到了很大的改善。     

低温硅双极晶体管电流增益研究

着重分析了多晶硅发射极对提高电流增益的作用和低温下集电区中性杂质碰撞电离引起的电流倍增效应，导出多晶硅发射极晶体管电流增益的表达式，很好地解释了实验结果。     

掺砷多晶硅发射极RCA晶体管

研究了掺砷多晶硅发射极RCA晶体管的工艺实验技术.以先进多晶硅发射极器件制备工艺为基础,在淀积发射极多晶硅之前,用RCA氧化的方法制备了一层超薄氧化层,并采用氮气快速热退火的方法处理RCA氧化层,制备出可用于低温超高速双极集成电路的掺砷多晶硅发射极RCA晶体管.晶体管的电流增益在-55-+125℃温度范围内的变化率小于15%,而且速度快,发射区尺寸为4×10μm2的RCA晶体管其特征频率可达3.3GHz.     

选择离子注入集电极技术研究

为提高超高速双极晶体管的电流增益 ,降低大电流下基区扩展效应对器件的影响 ,将选择离子注入集电区技术 (SIC)应用于双层多晶硅发射极晶体管中。扩展电阻的测试结果显示出注入的 P离子基本上集中在集电区的位置 ,对发射区和基区未造成显著影响。电学特性测量结果表明 ,经过离子注入的多晶硅发射极晶体管的电流增益和最大电流增益对应的集电极电流明显高于未经离子注入的晶体管。因此 ,在双层多晶硅晶体管中采用 SIC技术 ,有效地降低了基区的扩展效应 ,提高了器件的电学特性。     

掺砷多晶硅发射极RCA晶体管

研究了掺砷多晶硅发射极RCA晶体管的工艺实验技术.以先进多晶硅发射极器件制备工艺为基础,在淀积发射极多晶硅之前,用RCA氧化的方法制备了一层超薄氧化层,并采用氮气快速热退火的方法处理RCA氧化层,制备出可用于低温超高速双极集成电路的掺砷多晶硅发射极RCA晶体管.晶体管的电流增益在-55—+125℃温度范围内的变化率小于15%,而且速度快,发射区尺寸为4×10μm2的RCA晶体管其特征频率可达3.3GHz.     

低温大注入多晶硅发射极硅双极晶体管电流增益的定量模拟

已有的理论和实验都已证明，多晶硅发射极硅双极晶体管适合于低温工作，但至今为止，其完整的大注入时电流增益的理论分析还不成熟，特别是进行定量的计算。本文定量地模拟了低温７７Ｋ和常温３００Ｋ下多晶硅发射极硅双极晶体管电流增益与集电极电流密度的关系，并且分析了低温和常温下决定该晶体管电流增益大注入效应的主要物理效应。     

多晶硅发射极双极晶体管的工艺设计及计算机模拟

在简要分析多晶硅发射极双极晶体管特点的基础上，根据国内现有的双极工艺水平，设计了用于制备多晶硅发射极双极晶体管的工艺流程，并给出了一个最小尺寸晶体管的版图，最后对设计的多晶硅发射极晶体管的频率特性进行了模拟。     

多晶硅发射极NPN管的辐射效应研究

为了研究多晶硅发射极双极晶体管的辐射可靠性,对多晶硅发射极NPN管进行了不同偏置条件下⁶⁰Co γ射线的高剂量率辐照试验和室温退火试验。试验结果表明,辐射后,基极电流IB显著增大,而集电极电流IC变化不大;反偏偏置条件下,IB的辐射损伤效应在辐射后更严重;室温退火后,IB有一定程度的持续损伤。多晶硅发射极NPN管与单晶硅发射极NPN管的辐射对比试验结果表明,多晶硅发射极NPN管的抗辐射性能较好。从器件结构和工艺条件方面,分析了多晶硅发射极NPN管的辐射损伤机理。分析了多晶硅发射极NPN管与单晶硅发射极NPN管的辐射损伤区别。     

Effect of emitter contact materials on high-performance verticalp-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements     

Trade-off between emitter resistance and current gain inpolysilicon emitter bipolar transistors with intentionally growninterfacial oxide layers

Experimental measurements of emitter resistance and current gain in polysilicon emitter bipolar transistors that have received annealing to break up an intentionally grown RCA oxide interfacial layer are presented. An anneal of 900°C for 10 min in a nitrogen ambient of the interfacial layer prior to polysilicon doping resulted in a decrease in emitter resistance by approximately a factor of 5, with an increase in base saturation current of only 25% while still maintaining a current gain of around 500. The authors believe that this is the largest trade-off in emitter resistance versus current gain demonstrated so far for polysilicon transistors with an RCA interfacial layer. These results support a theory previously proposed by the authors (1991) predicting that significant trade-offs between emitter resistance and current gain can be obtained if an intentionally grown interfacial oxide layer in polysilicon emitter bipolar transistors is annealed so as to induce only partial breakup such that most of the layer remains intact     

基于Matlab的基极电流理想因子提取方法研究

采用Matlab数字分析方法,结合多晶硅发射极双极器件基极电流的构成情况,阐述了不同理想因子电流成分分离的基本原理和数学方法。利用该方法分析了多晶硅发射极双极器件在正向大电流激励下的电参数退化过程中不同理想因子基极电流的变化情况,分析了导致各电流分量变化的物理机制。该理想因子提取方法普遍适用于各类双极型器件。     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Optimization of a 0.6 μm, single polysilicon emitter bipolar technology versus narrow emitter effects

A novel 0.6 μm, single polysilicon emitter bipolar technology has been optimized in order to reduce the consequences of narrow emitter effects (NEE) appearing at the laterals of the emitter area. The primary technological mechanisms of these effects have been studied and differentiated for this technology. They have been found to be the polysilicon over-etch into the underlying silicon, the pedestal oxidation, both of them in the area of the extrinsic base implantation, and the extrinsic base lateral diffusion. Designs of experiments techniques have been used in order to study all these technological elements and their effect on the final performance of the transistors. Common emitter current gain variation versus emitter width has been studied by means of test structures and an optimization method is proposed. Lateral diffusion of extrinsic base has been identified as main source of NEE in this technology, which reduces the transistors current gain. Pedestal oxidation has been identified as secondary source of these effects, acting in an opposite way of lateral diffusion increasing the transistors current gain. This opposed effects have been tuned in the technological optimization to minimize the NEE by means of a mutual compensation.