一种用于THD优化的模拟乘法器设计

为有效地提高有源功率因数校正控制器(APFC)[1]性能,设计了一种用可控电流法实现,可应用于连续/临界型(CCM/DCM)升压(BOOST)模式APFC的模拟乘法器.该乘法器有较好的线性特性,线性范围达到0~3V,与传统方法相比,特别嵌入了总谐波失真(THD)优化电路,从而达到最优化输入电流THD,提高功率因数的目的.最后给出了具体的乘法器电路图和仿真结果.     

一种用于PFC的模拟乘法器设计

为了实现变频控制,产生一个与输入信号同频同相的电压信号,使输入电流跟随输入电压,设计了一种基于BCD工艺的模拟乘法器,并阐述了该电路设计的工作原理和结构.该乘法器应用于电流控制的功率因素校正电路,具有0～3 V的输入信号范围,采用上华0.6 μm BCD工艺设计,并用Cadence spectre仿真器进行仿真.仿真结果表明,输出波形是一个半正弦波,并且和输入同频同相,幅度达到1.2 V.     

单相SVG的基波无功电流跟踪算法

作为改善电能质量的一种重要手段,静止无功发生器SVG要求快速的检测出负载电流中的无功分量.本文针对直接电流控制的用户端单相SVG,提出一种新的单相无功电流的跟踪算法,该方法通过在一个计算周期内基波周期前后一段数据的比较来快速跟踪无功电流.仿真表明该方法正确可行.仿真波形可以看出,在一个周期内可以实现对无功电流的准确提取,而且对电流变化跟踪效果好,防干扰能力强.算法简单快速,只需两个乘法器,且易于实现.     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

基于平方根电路的电流模式乘法/除法器的实现

根据MOS管的跨导线性原理,设计了一个电流模式平方根电路.以该电路为基本模块,综合设计出一种新颖的电流模式乘法/除法器.采用TMSC 0.35 μm CMOS集成工艺,对设计出的电路进行PSPICE仿真测试.结果表明,提出的电路具有带宽宽、功耗低、线性度好等优点,可以作为一个基本模块在电流模式电路中使用.     

模拟乘法器提高高边电流检测的测量精度

将模拟乘法器和高边电流检测放大器相结合,能够在笔记本电脑或其他便携仪器中实现电池充、放电电流的测量.本文讨论将ADC的基准电压加到模拟乘法器的一个输入端,以提高电流测量精度的方法.     

电流型CMOS多值乘法器分析与芯片的设计

本文以电流型ＣＭＯＳ电路为基础，提出了种一高速、高集成度的多值乘法器设计方案，讨论了多值乘法器与集成度、速度和精度的关系，同时用改进ＣＭＯＳ工艺实现了３×３位８值乘法器的设计，得到了较理想的结果。     

一种高阶电流模式滤波器的系统设计方法

提出了一种通用高阶电流模式滤波器系统综合设计理论和方法,该方法将高阶通用电流模式滤波器的传递函数分解为n个无损积分器级联的形式.文章给出了基于MOCCCII实现的高阶通用电流模式滤波器,电路结构简单,仅由n 1个有源器件和接地电容构成.通过改变输入电流的接入方式和接入数目就可以实现不同类型的滤波功能.面向实际电路完成Pspice仿真.     

最少元件的通用电流模式滤波器

在电流控制电流传输器的基础上采用交叉耦合电流镜技术实现了多输出端口电流控制电流传输器(MOCCCII)。并利用该器件设计出一种结构简单的双二阶通用电流模式滤波器。该滤波器结构简单,仅包含2个有源器件,2个接地电容,并可通过改变外部输入电流的接入方式和接入数目,在同一输出端和不同输出端分别实现多种滤波功能。完成了实际电路的PSPICE仿真,结果表明提出的电路正确有效。     

利用简单电路提高传统PFC控制器性能

典型的两级离线PFC PFC离线功率转换器系统通常设计为两级级联型.第一级为一个升压转换器,这是因为该拓扑结构拥有连续输入电流(通过使用乘法器可实现电流波形控制)以及可实现近似单位功率因数的平均电流模式控制.但是,升压转换器需要一个比输入电压更高的输出电压,和另外一个将输出电压降压至可用电压等级的转换器(见图1).     

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.     

A one volt four-quadrant analog current mode multiplier cell

This paper describes a four-quadrant analog multiplier cell that can operate below one volt dc bias. This new multiplier cell is specially designed for low voltage portable communication equipment. The multiplier cell consists of two translinear loops. We have operated this new multiplier cell at as low as 0.8 V. With the exception of the low voltage operation, the output current of the multiplier cell is a true product of the input currents, and there is no limitation on the input dynamic range as with the conventional Gilbert cell     

A ± 0.75-V Compact CMOS Class-AB Current-Mode Exponential Variable Gain Amplifier

In this brief, a novel class-AB implementation of a current-mode exponential variable gain amplifier (VGA) is presented. The VGA is based on a novel current amplifier circuit implemented by multicoupled MOS translinear loops operating in strong inversion and saturation. The gain is conveniently configured for performing a pseudo-exponential approximation leading to a very compact design since an extra multiplier is not needed. Moreover the VGA can operate with very low voltage and power efficiency. Measurement results from a fabricated prototype in a 0.5-mum n-well CMOS technology reveal gain control up to 12 dB with errors less than plusmn0.5 dB and power consumption of 375 muW for a supply voltage of plusmn0.75 V.     

一种用于APFC的模拟乘法器设计

在有源功率因数校正技术(APFC)中,通过对乘法器的输出与电感电流的峰值比较,控制功率开关管的开启与关断,使输入电流峰值包络跟随输入电压,功率因数理论上为单位值。而提高乘法器的线性度,减小非线性误差成为研究模拟乘法器的一个重要方向。本文提出的模拟乘法器采用有源衰减器显著的增大了输入信号电压范围,更重要的是在有源衰减电路中引入负反馈有效的减小了乘法器的非线性误差。基于CSMC 0.5um BCD工艺,采用Hspice进行仿真验证,在电源电压5V条件下,乘法器的一输入端的输入范围为0~2V,非线性误差小于0.6%,另一输入端的输入范围为1~4V,非线性误差小于0.3%。总谐波失真小于1.8%。     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

Class-AB Flipped Voltage Follower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications

In this paper, a class-AB flipped voltage follower cell with high current driving capability is proposed. The proposed flipped voltage follower (FVF) cell offers increased current sourcing capability and large input/output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between output and ground terminals to increase the current sinking capability and to reduce the output resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.

     

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 μm AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

High Frequency and High Precision CMOS Half-Wave Rectifier

In this paper, a new high frequency and high precision half-wave rectifier circuit which is very suitable for CMOS technology implementation is presented. The system comprises a voltage to current converter, a dual output precision current-mode half-wave rectifier, and two current to voltage converters. An input voltage signal is converted into a current signal by using a current conveyor and a MOS resistor. The current signal is rectified using a dual output class-AB precision rectifier cell and then converted into two output voltages by using grounded MOS resistors. This class-AB current-mode precision rectifier is employed for providing high frequency performance. Simulated rectifier results based-on a 0.5 µm CMOS technology with ±1.2 V supply voltage demonstrates very high operating frequency, very precise rectification and good temperature stability.