IC测试系统精密定时器的新结构

讨论了一种适合于VLSI的精密定时子系统的新结构.该结构将定时计数器分为高速和低速两部分,低速部分采用存储器代替分散的寄存器,既有利于集成,又降低了系统的成本.同时,新的精密定时子系统还解决了定时中不完整周期的问题.     

综合型精密制造技术实验教学平台研制与应用

为满足高等工程教育实验教学需要,需要建立综合型精密制造技术教学实验平台。文中搭建五轴联动运动台结构及其电控系统,设计了多种超精密抛光及测试子系统,包括气囊抛光子系统、磁射流加工子系统、超声振动辅助子系统、压痕子系统、材料硬度与表面检测子系统、材料亚表面损伤检测子系统,实现了多种加工与检测的教学实验功能。该综合型精密制造教学实验平台具有适用范围广、易组合扩展等特点,为“新工科”背景下高等工程教育实验教学改革和先进制造领域技术研究提供了良好的硬件平台。     

精密定时电路

本文提出一种耗电省,设置时间十分方便的精密定时电路的设计思想,并介绍一个定时时间在1～99分钟的精密定时电路实例。 1～99分钟精密定时电路如图1所示,它主要由     

基于PAM分解的高阶部分响应CPM信号盲定时同步算法

针对高阶部分响应连续相位调制(CPM)信号盲定时同步中存在定时精度较低以及容易出现假锁等问题,该文从脉冲幅度调制(PAM)分解的角度出发,设计了一种新的适用于高阶部分响应CPM信号的定时同步器结构,并在此基础上结合基于马尔科夫链模型的定时假锁检测方法,提出了一种适用于高阶部分响应CPM信号的盲定时同步算法.该算法通过对CPM信号的PAM脉冲进行优化处理,有效减少了匹配滤波器以及网格状态的数目,同时使用辅助定时误差检测器和假锁检测器来实时监测假锁现象.理论分析和仿真结果表明,对于四阶部分响应CPM信号,在低信噪比并存在较大初始定时误差条件下,该算法也能够实现精确快速的定时同步.     

色散管理孤子系统定时抖动的分析计算

利用两种方法研究了脉冲形状为高斯型的色散管理孤子系统定时抖动。利用微扰变分方法推导出光通信系统存在滤波器和自发辐射噪声的情况下,孤子参数演化的动力学方程,得出了定时抖动的表达式,并对其进行仿真,发现定时抖动来源于放大器噪声、频率偏移等,啁啾的符号和滤波器对系统总的定时抖动也有一定影响。再利用矩方法对色散管理孤子系统定时抖动进行了分析,两种方法得到的结果一致。     

GSM网的时钟同步问题

探讨了湖北省GSM网的交换子系统从数字同步同获取定时基准、实现同步的措施,即定时楼内分配、局间分配和提高交换点的定时性能。     

GSM网的时钟同步问题

探讨了湖北省ＧＳＭ网的交换子系统从数字同步网获取定时基准,实现同步的措施,即定时楼内分配,局间分配和提高交换的定时性能。     

基于训练序列的OFDM系统定时同步改进算法

本文从OFDM系统模型和同步技术作为切入点重点分析研究了基于训练序列的OFDM系统定时同步算法,针对基于SC算法构造的训练序列帧结构及所采用的定时估计算法会造成定时同步位置具有峰值平台、定位点模糊、定时同步不够精确的缺点,提出了一种基于SC算法的改进型训练序列帧结构及改进算法。该算法对SC算法中训练序列前后两部分的搬移重复结构进行改进,构造了前后两部分呈中心对称的训练序列帧结构。改进算法不再采用SC算法中训练序列的后半部分来定义能量函数,而是采用整个训练序列长度来定义能量函数,从而构建同步度量函数,找到最佳定时同步估计点并完成定时同步。理论分析和仿真结果表明,改进算法解决了SC算法定时同步估计位置模糊、定时同步不精确的问题,改进后的算法能够确保定时同步的精确性。      

基于ISP芯片的汉字定时显示装置的设计

介绍了一种带定时的精密可编程汉字显示装置,重点介绍了运用新型在系统可编程逻辑器件ISP芯片来实现可编程汉字定时显示的方法。     

SJT—1型低速精密三轴伺服转台

本转台是低速高精度伺服转台.该转台用复现空间飞行器如卫星、导弹等姿态的半物理仿真装置.系统结构中采用了分装式滚珠轴系,精密电位计,增量式圆光栅,脉冲调宽电路,8089单片机及386微机等技术.测试结果表明系统的定位精度、重复性及低速平稳性指标均超过了设计要求.本转台的特点是低速(0.001度/s),高精度(内轴定位精度在轴上最大值为1.5s),     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.     

基于Verilog的模拟前端时序的实现方法

针对如何高精度、高速实现模拟前端时序的问题,提出了一种用于平板探测器的模拟前端时序的Verilog实现方法。Verilog语言的编程整体上采用模块化设计,主要包含电荷采集模块、数据读出模块和计数器模块。利用锁相环技术设置各模块不同的时钟信号,通过编写有限状态机和改进型计数器实现各模块的时序。仿真结果表明,该编程方法满足了时序高精度实现的需求,具有运行速度快、灵活性高等特点,达到了预期效果。     

PCM串行数据流同步时钟提取设计

为了产生语音调度系统中数据接收端异步接收PCM30／32路一次群串行数提流所需同步时置瑚目的,采用以分频计数器为基础模块,辅以相位校正和误校正处理模块从已知速率PCM数据流中提取同步时钟信号的方法,利用可编程逻辑器件和VerilogHDL硬件描述语言对该方法进行实现和仿真验证。结果表明该方法能够有效地利用已有串行数据流产生具备合适相位的同步采样时钟信号。     

Iterative skew minimization for low swing clocks

This paper presents a new methodology that implements a low swing clock tree. For low power IC design, low swing clock trees are one of the known techniques to lower the overall power dissipation through decreasing the power consumption of the clock network, while trading off the clock skew, local timing (slack) and the variation-tolerance (due to decreased noise margin). In this paper, an iterative skew minimization scheme for low swing clock trees is proposed via in-place buffer sizing considering multiple process corners. The proposed approach can preserve the power savings of the low swing clock tree implementation across multiple process corners. The effect of the decreased clock swing on the local timing is analyzed: The degradation in the timing slack is shown to be insignificant due to bounded clock slew eliminating most of the timing degradation on the clock network or the logic paths induced by decreased clock swing. The experimental results show that the proposed methodology can achieve an average of up to 11% power savings, with a skew degradation of less than 5% compared to the original full-swing clock tree, satisfying a practical skew budget. The proposed scheme is highly practical as it only performs in-place buffer sizing on the original clock tree.     

基于NI MULTISIM 11.0软件的数字钟设计与仿真

数字电子钟是一个对标准频率(1Hz)进行计数的计数电路。由振荡电路形成秒脉冲信号,秒脉冲信号输入计数器进行计数,并把累计结果以"时"、"分"、"秒"的数字显示出来。秒计数器电路计满60后触发分计数器电路,分计数器电路计满60后触发时计数器电路,当计满24小时后又开始下一轮的循环计数。由振荡电路、计数器、数码显示器、校时电路、整点报时电路等几部分组成。     

The effect of propagation delay uncertainty on the speed oftime-of-flight digital optoelectronic circuits

Time-of-flight synchronization is a new digital design methodology for optoelectronics that eliminates latches, allowing higher clock rates than alternative timing schemes. Synchronization is accomplished by precisely balancing connection delays. Circuits use pulse-mode signaling and clock gates to restore pulse timing. Many effective pipeline stages are created within combinational logic without extra hardware bounding the stages. Time-of-flight design principles are applicable to packet routing and sorting processors for optical interconnection networks. Circuits are unique because the clock rate is limited primarily by imprecision in propagation delay rather than absolute delay, as in circuits with latches. We develop a general model of delay uncertainty and focus on the effect that static and dynamic uncertainty accumulated over circuit paths has on the minimum feasible clock period. We present a method for traversing the circuit graph representation of a time-of-flight circuit to compute arrival time uncertainty at each pulse interaction point. Arrival time uncertainties give rise to pulse width and overlap constraints. From these constraints we formulate a constrained minimization to find the minimum clock period. We demonstrate our method on circuits implemented with 2×2 electro-optic switches and optical waveguides and find the electronic component of path uncertainty frequently limits speed     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

基于BLF时钟的RFID低功耗数字基带设计

提出了一种符合ISO/IEC 18000-6C协议中关于时序规定的射频识别(RFID)无源标签芯片低功耗数字基带处理器的设计.基于采用模拟前端反向散射链路频率(BLF)时钟的方案,将BLF的二倍频设置为基带中的全局时钟,构建BLF和基带数据处理速率之间的联系;同时在设计中采用门控时钟和行波计数器代替传统计数器等低功耗策略.芯片经TSMC 0.18 μmCMOS混合信号工艺流片,实测结果表明,采用该设计的标签最远识别距离为7 m,数字基带动态功耗明显降低,且更加符合RFID协议的要求.     

MCS-51单片机中软时钟设计的优化方法

根据MCS-51单片机内部定时计数器的特点,提出一种通过对定时计数器中断间隔时间进行累加的软时钟设计方法,并在此基础上提出通过改变时间处理方式的进一步优化方法。此方法不仅简化了程序设计,节省了硬件开销,而且提高了电脑时钟的定时精度,具有广泛的应用价值。     

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test equipment (ATE), our method facilitates the test of the rated-speed timing and allows performance binning. A CMOS implementation of the DFT hardware with 50 ps timing accuracy is presented. To demonstrate the effectiveness of the technique we designed a 16-bit, 1.4 GHz pipelined multiplier as a test vehicle. Simulations using a test clock frequency much lower than the rated clock frequency show that delay faults of sizes as small as 50 ps are detected and that the new test technique provides correct performance binning.