IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

Investigation on copper diffusion depth in copper wire bonding

Due to the dramatic price increase of precious metals, the replacement of Au with Cu in wire bonding has become an emerging trend for IC packaging nowadays. Similar to the Pb-free soldering transition, such a replacement is not just a simple drop-in material change. Comprehensive processing and reliability investigations are required before a mass production of electronic devices with Cu wire bonding can be implemented. However, among the existing studies on Cu wire bonding, it appears that most researchers just focused on issues above the wire bond pads. In fact, the Cu in the wire bonds may diffuse into the Si chip and impose reliability threats to the electronic devices. So far there was no research on the Cu-to-Si diffusion issue in Cu wire bonding. In this paper, an experimental study on the Cu-to-Si diffusion in Cu wire bond is reported. The Cu diffusion depth was characterized with the secondary ion mass spectrometry (SIMS) technique. Specimens with various configurations were designed and fabricated to investigate the effects of several parameters on the Cu-to-Si diffusion depth. The issues of concern include the amount of Cu supply, the bond pad deformation, and the barrier layer under the bond pad. In addition, some samples with conventional Au wire bonding were fabricated and tested in parallel for comparison.     

Reliability considerations for ESD protection under wire bonding pads

We have developed a configuration for diode-based electrostatic discharge structures that can be reliably placed under the metal stack of an integrated circuit wire bonding pad, thereby reducing the die area consumed for ESD. Prototype structures from both three- and four-level CMOS processes were assembled using gold ball and aluminum wedge bonding, respectively. Visual inspections after bonding found nothing that would compromise the integrity of the structure. Electrical tests found no failures from the ESD structure placement under the pad for over 8000 pads in the three-level metal and over 7000 pads for the four-level metal process. Structures under the pads pass full product-level qualification procedures.     

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.     

Capacitor-couple ESD protection circuit for deep-submicronlow-voltage CMOS ASIC

Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit. Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected     

On-chip ESD protection design by using polysilicon diodes in CMOSprocess

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC     

An investigation on the plasma treatment of integrated circuit bond pads

Integrated circuit (IC) bond pads play an important role in the wire bond reliability of the microelectronic devices. Being the device’s only electrical connection to the package and electronic systems, it is mandatory that the bond pads are free of contaminants and possess excellent bonding characteristics. Contaminants such as oxides and organic residues impair the bondability to a considerable extent and are very resistant to conventional wet cleaning methods. In this paper, we report the effects of an Ar/H₂ plasma treatment on the surface chemistry and morphology of IC bond pads. Surface and sub-surface chemical analyses have been conducted using Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). Results reveal that the oxygen level of the bond pad surface has decreased significantly after the plasma treatment. Although the treatment has successfully removed the surface crystallites on the bond pads on prolong etching; however, the aggressive process has also damaged the passivation layers that surround the pad areas.     

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V_SS, negative-to-V_SS, positive-to-V_DD, and negative-to-V_DD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.     

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.     

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

InSb红外探测器芯片金丝引线键合工艺研究

InSb红外探测器芯片镀金焊盘与外部管脚的引线键合质量直接决定着光电信号输出的可靠性,对于引线键合质量来说,超声功率、键合压力、键合时间是最主要的工艺参数。从实际应用出发,采用KS公司4124金丝球焊机实现芯片镀金焊盘与外部管脚的引线键合,主要研究芯片镀金焊盘第一焊点键合工艺参数对引线键合强度及键合区域的影响,通过分析键合失效方式,结合焊点的表面形貌,给出了适合InSb芯片引线键合质量要求的最优工艺方案,为实现InSb芯片引线键合可靠性的提高打下了坚实的基础。     

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-/spl mu/m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I/sub t2/) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.     

Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

A low-voltage triggering SCR for on-chip ESD protection at outputand input pads

A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V     

Complementary-SCR ESD protection circuit with interdigitatedfinger-type layout for input pads of submicron CMOS IC's

A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6 μm CMOS SRAM technology with the LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup under 5 V VDD operation by means of a base-emitter shorting method. To compensate for the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by the base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform at high ESD failure threshold in small layout areas, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications     

A vision system for inspection of ball bonds and 2-D profile ofbonding wires in integrated circuits

A critical stage in the manufacture of integrated circuit devices is inspection of the wire bonds which connect the chip to the lead fingers of the device. This paper describes a vision system for 1) automatic inspection of that part of the wire bond where the wire connects to the bond pad on the chip and 2) inspection of the 2-D profile of the bonding wire. A popular type of bonding (connection to bond pad) known as “ball bond” is considered here. Using two-dimensional images taken from the top of the IC wafer, the system determines several geometric measures which are important in determining the quality of the bond and the wire. These include the center and the boundary of the bond as well as the degree of straightness of the wire. A bond shape analysis based on the parameters of the best fitting ellipse to the bond is developed. The bonding process can be monitored through tracking the statistics of the bond shape measures. The system has been tested in a prototype manufacturing environment with excellent results