一种低功耗射频无线收发芯片基带控制器

设计了一种应用于射频无线收发芯片的数字基带控制器,采用中芯国际0.18μm CMOS工艺设计。该基带控制器系统主要包括接口电路、组帧电路、解帧电路以及核心控制处理器,可实现SPI通信和多种收发功能操作。基带控制器最终被集成到射频收发机芯片中并进行了流片验证,测试结果显示,基带控制器面积为0.54mm2,所有功能工作正常,实测功耗0.59mW。     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

一种超低功耗无源超高频射频识别标签芯片的设计与实现

本文提出了一种符合ISO18000-6B协议的无源超高频射频识别标签芯片设计。该芯片包括了射频/模拟前端,数字基带和512比特的EEPROM存储器。采用肖特基二极管来提高整流器的功率转换效率。详细阐述了基于峰值电流源的参考电压源的设计,该电路结构简单,并且可以满足低压、低功耗的设计要求。为了降低功耗,模拟模块工作在1v以下电源电压,并采用了一些低功耗的设计方法进一步降低数字基带的功耗。整个标签芯片采用TSMC 0.18um CMOS工艺实现,芯片尺寸为800*800um2。测试结果表明芯片的总功耗为7.4uW,灵敏度达-12dBm。     

UHF RFID标签芯片模拟射频前端设计

对射频识别标签芯片系统结构及工作原理进行分析,设计应用于符合ISO18000—6C／B两种标准的UHFRFID标签芯片的模拟射频前端,主要包括整流电路、稳压电路、调制／解调电路、上电复位及时钟产生电路。模拟射频前端芯片采用TSMC0．18μm CMOS混合信号工艺流片验证。测试结果表明,所研制的模拟射频前端性能满足UHF RFID标签芯片系统要求。     

RFID标签芯片的最新研究进展

射频识别(RFID)系统是一种具有广泛应用前景的自动识别系统。近年来,射频识别技术以快速增长趋势在供应链、门禁、公交系统、行李跟踪等领域获得了广泛的应用。文章详细论述了不同频段RFID标签芯片的最新研究进展,对标签芯片的核心模块射频模拟前端、数字控制器、存储器的研究及发展趋势进行了分析。最后,讨论了标签芯片的发展方向。     

一种低功耗UHF RFID标签数字基带处理器

超高频射频识别(UHF RFID)电子标签的低功耗设计是当前的研究热点与难点。数字基带部分的功耗占芯片总功耗的40%以上,而时钟模块的功耗约为基带部分的50%。针对此问题,设计了一种兼容EPCTM C1 G2/ISO 18000-6C协议的新型UHF RFID标签数字基带处理器。围绕时钟信号设计了新型数字基带架构,引入局部低功耗异步电路结构,并采用模块时钟的门控动态管理技术,尽可能降低功耗。该数字基带电路在FPGA上完成了功能实测,采用SMIC 0.18 μm CMOS完成了芯片级的逻辑综合及物理实现。结果表明,版图面积为0.12 mm²,平均功耗为 8.8 μW。     

超高频无源电子标签芯片的模拟电路设计

电子标签芯片是无线射频识别(RFID)技术的核心,其模拟电路的设计十分关键。基于ISO/IEC18000-6C标准,以设计出符合标准的标签芯片为设计目标,超高频(UHF)无源电子标签芯片模拟电路被提出。它分为电源产生电路、调制解调电路以及上电复位模块等模块。设计结果表明,设计的电路具有很高的整流效率,满足了设计需求。     

无源UHF RFID芯片中低功耗基带处理器的设计

对UHF RFID标签芯片的数字基带处理器结构及工作原理进行了分析。该基带处理器兼容ISO18000-6C协议。采用一系列先进的低功耗技术,如门控时钟技术、减小工作电压、降低时钟频率等,以降低无源射频识别标签的功耗。整个标签芯片采用TSMC 0.18μm 1P5M嵌入式EEPROM混合CMOS工艺实现。测试结果表明,该芯片正常工作的最低电压仅为1 V,平均电流为6.8μA,功耗为6.8μW,面积仅为150μm×690μm。     

低压低功耗无源UHF RFID标签芯片模拟前端电路的设计

本文从设计符合EPCTM C1G2协议的超高频无源射频识别标签芯片的角度出发,对RFID标签芯片模拟前端电路进行设计.通过对各个关键电路的功耗与电源进行优化,实现了一个符合协议要求的低电压、低功耗的超高频无源RFID标签芯片的模拟前端.该UHF RFID标签模拟前端设计采用SMIC 0.18 μm EEPROM CMOS工艺库.仿真结果表明,标签芯片模拟前端的整体功耗控制在2.5 μW以下,工作电源可低至1 V,更好地满足了超高频无源射频识别标签芯片应用需求.     

可适应多种时序情况的DMA控制器设计

在以SD卡为图像存储器件的图像协处理器中,基带芯片和SD卡控制器在速度上的差异经常会导致数据传输错误。为解决此问题,设计了一种可适应多种时序情况的DMA控制器。该DMA控制器的状态机,一方面对基带芯片和SD卡控制器的操作请求进行仲裁,在响应基带芯片请求的同时,适当推迟SD卡控制器的请求;另一方面对DMA读写的数据进行计数,并以此判断SD卡的一次多块读或多块写操作是否完成;最后对基带芯片和SD卡控制器的速度做出判断,必要时暂停速度较快一方的操作。实际工作表明,该DMA控制器能够在基带芯片和SD卡控制器之间正确传输数据并使读写SD卡的速度达到210 kB/s。     

CDMA2000基带信号发生器的FPGA+DSP实现

提出了基带信号发生器中CDMA2000无线传输技术的下行链路基带处理方案，给出了其数字基带处理原理框图，并详细介绍了设计过程中涉及的各种CDMA关键技术及其软硬件实施方案。     

蓝牙主控制器接口简析

介绍了蓝牙主控制器接口(HCI)规范的内容,着重描述了对HCI的功能分析。HCI提供对基带控制器和链路管理器的命令接口以及对硬件状态和控制员的访问。该接口还提供对蓝牙基带的统一访问模式。     

Validation Study of LPDDR2 SDRAM Based on TD-LTE Baseband chip

In recent years,as China has finished the updating of the fourth generation of network,for guaranteeing the information security of the state,communication chip with complete independent intellectual property right must be possessed to support the advancement of such project.TD-LTE Baseband Chip is a super-large-scale integrated circuit designed basing on SOC,which needs to carry out coding,etc to the transmitted baseband signal,or carry out decoding,etc to the received baseband signal.LPDDR2 SDRAM is used in the chip design process due to its low power dissipation,high capacity and high reliability.As PHY in the controller architecture of LPDDR2 SDRAM adopts hard core design,it cannot be achieved in Virtex-7 2000T prototype verification platform.This design mainly builds on such prototype verification platform to propose the verification scheme of LPDDR2 SDRAM controller in TD_LTE baseband chip,so as to guarantee that prototype verification in FPGA can be carried out by TD_LTE baseband system,and meanwhile high capacity storage space can be provided to the system.     

Highly-integrated analog baseband for 3G WCDMA featured cellular phones

This paper presents an analog baseband circuit which is fully integrated in a 3G WCDMA digital baseband controller (modem) together with an application (multimedia) processor targeted featured cellular phones. The analog baseband is made by two (I and Q) 8b+ Analog-to-digital converters (ADCs), two (I and Q) 10b digital-to-analog converters with filters, a 10b auxiliary ADC, and a common circuit for the generation of an accurate bandgap reference voltage and biasing currents. To avoid performance degradations caused by crosstalk among the converters or from the nearby digital baseband activity, several design and layout precautions have been taken. All performance are guaranteed in mass production from ?40 to +130 °C. The analog baseband converters are designed at 2.5 V supply in a 65 nm CMOS process with double oxide and MIM capacitor options. Total power consumption and area are 32.8 mW and 1.8 mm², respectively.     

基带芯片物理层控制方案的设计

对多核基带芯片物理层控制方案进行了简单的讨论,提出了一种用于GSM移动终端基带芯片物理层控制(L1C)的方案,根据GSM的帧结构设计了基时钟电路,并以物理层信号处理流程为依据,建立了物理层上下行的调度时序,初步完成了基带芯片SoC系统多核之间的任务调度和时序控制。     

Low-power and high-quality signal transmission baseband LSIC forpersonal communications

This paper presents a very low power consumption one-chip baseband large-scale integrated circuit (LSIC) for personal communication terminals. It comprises a π/4-shift QPSK modem, an adaptive differential pulse code modulation (ADPCM) codec, a time division multiple access time division duplex (TDMA-TDD) controller and a link access procedure for a digital cordless (LAPDC: Layer-2 protocol) controller. The developed LSIC meets all the specifications of the personal handy-phone system (PHS) standard. By employing a novel coherent demodulator and an ADPCM codec with a click noise suppressor, a higher quality voice transmission has been achieved in a fading environment. In addition, it has 61-kb/s data transmission capability to achieve wireless multimedia services based on PHS. Moreover, the novel circuit configurations of the modem, the ADPCM codec, the TDMA-TDD controller, and the LAPDC controller achieve significant power reduction of the baseband circuits (57.4 mW) of personal communication terminals. It enables very low power consumption wireless multimedia terminals to be achieved based on the PHS common air interface     

基于TMS320C6455 DSP的PCI接口设计

TMS320C6455是 TI公司的一款高性能数字信号处理芯片（DSP）,具有丰富的外部接口。本文介绍了该芯片外围设备组件互连（PCI）接口控制器的性能特点,DSP 内部的工作机制,地址映射方式,详细分析了2种工作方式的总线传输特点和性能,并给出了将其应用于卫星基带信号接收卡的设计实例。通过使用 TMS320C6455 DSP的 PCI控制器简化了硬件接口设计,具有灵活高效的特点,已在工程应用中取得了良好效果。     

智能化基带平台

介绍了一种智能基带平台,该平台借鉴了软件无线电的思想,通过FPGA和DSP芯片来构造一个具有通用性、可扩展性、可扩充性、灵活的多功能基带处理平台,经动态配置可以进行多模式、多速率工作。给出了设计框图和主要器件选择结果。介绍了几种典型应用模式,在实际工程中使用中取得了理想的效果。     

Noncoherent block detection in the presence of DC offset

In this paper, we deal with noncoherent detection of a digitally phasor block-modulated signal in the additive white Gaussian noise channel when a direct-current (DC) offset is present in the receiver baseband processing. By processing the received baseband signal block by block, a generalized linear transform is used to remove the offset prior to data detection, thereby releasing the succeeding detection process from the threat of DC offset. Operating on transform output blocks, a generalized maximum-likelihood scheme is developed for noncoherent data detection without a priori knowledge of channel amplitude and phase. When all the signaling blocks are confined within the space expanded by the basis vectors obtained from the onset-removal transform matrix, the proposed detection scheme can exploit the advantage of performing data detection and estimation on channel amplitude and phase jointly in the maximum-likelihood sense. It is analytically shown that the block detection scheme provides the bit error performance asymptotically approaching that of the corresponding ideal coherent phase-shift-keyed (PSK) detection in the absence of DC offset when the block length is increased. An iterative detection scheme is also modified from the block detection scheme to simplify the realization complexity. Both block and iterative detection schemes are shown to outperform the conventional training-sequence-aided PSK detection scheme under the same transmission throughput efficiency.