A 10-bit wide-band CMOS direct digital RF amplitude modulator

This paper describes a low-distortion wide-band CMOS direct digital RF amplitude modulator, which uses a 10-bit linear interpolation current-steering digital-to-analog converter (DAC) and a Gilbert-cell-based mixer to generate an amplitude modulated RF signal directly. The linear interpolation increases the attenuation of the DAC's image components. The reconstruction filter is, therefore, eliminated. The DAC's differential current signals are directly sent to the mixer, which improves the linearity of the modulated RF signal. Thus, the RF transmitter structure is simplified, and the low distortion is achieved. This modulator is suitable for system-on-chip (SOC) design and is easily scalable. The chip was fabricated in a 0.35-/spl mu/m 3.3-V double-poly triple-metal CMOS process. The core size of the chip is 0.52 mm/spl times/0.68 mm. With a 3.3-MHz modulation signal, a 50-MHz clock, and a 1-GHz carrier, the distortion components are below -53.81 dBc, and the attenuation of the image signal is 47.45 dB. The output power is -6.5 dBm, and the total power consumption is 159.8 mW.     

Direct digital-RF amplitude modulator in CMOS 90nm

Two different wireless transmitter topologies based on an direct digital-RF amplitude modulator (DAM) are presented: a polar modulator and a direct digital-RF IQ modulator prototype. The DAM consists of 255 basic cells digitally activated by an 8-bit amplitude code to shape a non-constant envelope RF output. The cells are segment-addressed resulting in a very compact 0.007 mm² chip area in CMOS 90nm. In order to reduce the spectral images due to the discrete-time to continuous-time conversion a 2-fold interpolation has been implemented. The DAM reaches a peak output power of 5 dBm at 2.45 GHz with 23% drain efficiency. Both direct digital modulator architectures fulfill WLAN 802.11g linearity constrains at 2.45 GHz.     

Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC

A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and can be monolithically integrated into advance digital VLSI systems. A fourth-order single-bit quantizer bandpass digital ΣΔ modulator is used preceding the DRFC, resulting in a high in-band signal-to-noise ratio (SNR). The out-of-band spectrally-shaped quantization noise is attenuated by an embedded semi-digital FIR filter (SDFIR). The RF output frequencies are synthesized by a novel configurable voltage-mode RF DAC solution with a high linearity performance. The configurable RF DAC is directly synthesizing RF signals up to 10 GHz in first or second Nyquist zone. The proposed DRFC is designed in 22 nm FDSOI CMOS process and with the aid of Monte-Carlo simulation, shows 78.6 dBc and 63.2 dBc worse case third intermodulation distortion (IM3) under process mismatch in 2.5 GHz and 7.5 GHz output frequency respectively.     

A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only     

A CMOS 5-V analog front end for 9600-bit/s facsimile modems

A CMOS 9600-b/s facsimile-modem analog front end was designed with the consideration that it be capable of being fabricated on the same chip with digital signal processing circuits. To achieve the dynamic range required in the high-speed QAM (quadrature amplitude modulation) modem environment with a single 5-V power supply, a fully differential architecture is used. The die area is 23 kmil/SUP 2/ and the power consumption is only 35 mW. The experimental results show that 76-dB dynamic range is achieved from the fully differential bandpass filter. The zero crossing detector in the MF-1 detection block can normally operate with -50-dBm input signal.     

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

基于光子芯片的微波光子混频器 （特邀）

提出了一种由光生本振单元和波长分离调制单元组成的微波光子混频方法,并在绝缘体上硅材料上设计实现了上述波长分离调制芯片。该芯片集成了硅基相位调制器、微环滤波器、光电探测器、光耦合器和光栅耦合器。实验搭建了基于该波长分离调制芯片的微波光子次谐波混频系统,结果表明,该微波光子混频器可以将6~16 GHz的RF信号变频到33~23 GHz。此外,针对实验系统中残留的混频杂散,分别提出了增加微环滤波器抑制比降低泄露光生本振强度和引入光移相器修正泄漏光生本振相位两种解决方案。通过仿真验证可知,引入光移相器的方法更为简单,更适合于光子集成芯片。     

A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler

This paper describes a novel monolithic low voltage (1-V) CMOS RF front-end architecture with an integrated quadrature coupler (QC) and two subharmonic mixers for direct-down conversion. The LC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunction with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps suppression of LO leakage at RF port. The circuit was fabricated in a standard 0.18-mum CMOS process for 5-6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below -110.7 dBm.     

All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters

A novel architecture for a fully digital wideband wireless transmitter is presented. The proposed structure replaces high-dynamic-range analog circuits with high-speed digital circuits and offers a simple and flexible architecture, which requires less area, consumes less power, and delivers higher performance compared to those of the conventional modulators used for wideband systems. The design is based on a standard 65-nm CMOS process and is suitable for integration with a digital signal processor, memory, and logic implemented in such a process. The presented transmitter is based on a novel digital quadrature modulator (DQM), which achieves digital modulation in a Cartesian coordinate system. The novel architecture employs a single converter, referred to as the differential-like digital-to-RF converter (DDRC), as it is based on fully digitally combining the quadrature baseband signals. The DDRC, at the heart of the DQM, combines functionalities of a mixer, a digital-to-analog converter, and an RF filter into a single circuit. The total area for the digital blocks is $0.04 hbox{mm}^{2}$, with a power consumption of roughly 5 mW. It is shown that the proposed transmitter meets the spectral mask, defined in the targeted IEEE 802.16e (WiMAX) standard, with a margin of 20 dB and achieves an error-vector-magnitude (EVM) performance of $-{hbox{36}} hbox{dB}$ with a margin of 6 dB.      

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

A GMSK modulator using a ΔΣ frequencydiscriminator-based synthesizer

This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of ΔΣ frequency discriminator (ΔΣFD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a ΔΣFD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-μm BiCMOS ΔΣFD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz     

All-digital PLL and transmitter for mobile phones

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.     

光载射频信号在多模塑料光纤中的传输特性研究

实验研究了光载射频信号在多模塑料光纤(POF)中的传输特性,将24GHz的正弦波信号与1.5Gbt/s的数字信号进行混频后再通过光强度调制器产生双边带调制光信号,将双边带调制信号通过多模POF发送至接收机,在接收机转化为24GHz的射频信号。实验结果表明,这种双边带调制的光载波射频信号可以在多模POF中传输50m后而功率代价可以忽略不计。     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

Integrated antenna with direct conversion circuitry for broad-band millimeter-wave communications

A compact integrated antenna with direct quadrature conversion circuitry for broad-band millimeter-wave communications is proposed. The conversion circuits include two even-harmonic mixers based on antiparallel diode pairs (APDPs). The equivalent circuit of the APDP derived here provides good agreement with the measured data from 17 to 23 GHz. Overall phase and amplitude imbalance between the in-phase/quadrature (I/Q) output channels are less than 1.2/spl deg/ and 1 dB at IFs of 10 and 100 MHz, respectively. An overall RF power conversion loss of 14.6 dB at the quadrature I/Q channels including the antenna is achieved in the frequency range from 39.75 to 40.25 GHz with a local oscillator (LO) power level of 11.8 dBm. LO leakages at 20 and 40 GHz are -31.5 and -44.8 dBm, respectively. In order to demonstrate the system capabilities for broad-band digital communication, a communication link is built with a pair of the proposed front-ends. Data transmission up to 1 Gb/s data rate for quadrature phase-shift keying modulation is demonstrated.     

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma–delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-${rm mu}{hbox{m}}$ CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.      

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

PWM方式输出合成语音

针对采用波形编码方式语音合成集成电路设计出的新型D/A转换方式,即利用脉冲宽度调制（PWM）技术,将数字语音信息直接转化成脉冲宽度调制波,通过低通滤波器可以恢复出模拟语音信号。本文所设计的数字脉冲宽度调制器采用CMOS工艺,适合于不同的语音合成集成电路。     

A 27-mW CMOS fractional-N synthesizer using digital compensationfor 2.5-Mb/s GFSK modulation

A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-μm CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH Σ-Δ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard