反应离子刻蚀硅槽工艺研究

在CMOS多晶硅刻蚀工艺的基础上进行工艺开发,采用氯气和溴化氢气体进行硅槽刻蚀。通过对功率、压力、气体流量等工艺参数拉偏,用扫描电子显微镜观察硅槽侧壁形貌,分析各参数在反应离子刻蚀中所起到的作用,得到对硅槽形貌影响较大的因素,最终得到一种能够与CMOS工艺兼容的硅槽刻蚀方法。该方法能够制作出深度6μm、深宽比4∶1、侧壁光滑的硅槽,可以用于光电继电器、硅电容等新型器件的研发。     

硅槽刻蚀技术中的源气体选择

源气体及组分的选择是硅槽刻蚀技术的关键因素。本文介绍了刻蚀过程中源气体及组分对硅的作用方式，从刻蚀速率、侧壁钝化、损伤、刻蚀均匀性等方面分析比较了近年来所出现的几种硅糟刻蚀用源气体及组分。     

硅槽刻蚀工艺研究

集成电路的发展使硅槽的应用越业越广泛，如硅槽隔离和槽电容等等，它们将使器件的性能得到很好的改善。     

硅的干法刻蚀简介

随着硅栅MOS器件的出现,多晶硅渐渐成为先进器件材料的主力军。除了用作MOS栅极之外多晶硅还广泛应用于DRAM的深沟槽电容极扳填充,闪存工艺中的位线和字线。这些工艺的实现都离不开硅的干法刻蚀技术其中还包括浅槽隔离的单晶硅刻蚀和金属硅化物的刻蚀。为了满足越来越苛刻的要求,业界趋向于采用较低的射频能量并能产生低压和高密度的等离子体来实现硅的干法刻蚀。感应耦合等离子刻蚀技术（ICP）被广泛应用于硅及金属硅化物刻蚀,具有极大技术优势和前景。     

用于自对准Si MMIC的等平面深槽隔离工艺(英文)

研究了在自对准硅MMIC中等平面深槽隔离工艺的实现。该工艺包括如下过程:首先应用各向异性刻蚀的Bosch工艺刻蚀出用于隔离埋集电极的1.6μm宽、9μm深的隔离槽,接着对隔离槽通过热氧化二氧化硅、淀积氮化硅和多晶硅的形式进行填充,然后再采用高密度等离子体刻蚀设备对多晶硅进行反刻,其刻蚀时间通过终点检测系统来控制,最后再刻蚀出0.8μm深的有源区硅台面和采用1.5～1.6μm厚的氧化层对场区进行填充,藉此来保证隔离槽和有源区处于同一个平面上。此深槽隔离工艺与目前的多层金金属化系统兼容,且该工艺不会造成明显的硅有源区台面缺陷,测试结果表明:在15 V下的集电极-集电极漏电流仅为10 nA,该值远低于全氧化填充隔离槽工艺的5μA。     

一种新的硅深槽刻蚀技术研究

本文报告了一种获得侧壁陡直的硅深槽新技术．实验中采用一种新材料──氮化锆（ＺｒＮ）作为反应离子刻蚀的掩模，所需掩模厚度约５００．采用氟基气体ＳＦ６作为刻蚀气体，并附加Ａｒ和Ｏ２，这样刻蚀过程中在槽的侧壁会形成氧化硅作为阻挡刻蚀层，结果得到了深约６μｍ，侧壁垂直接近９０°的硅深槽．     

RMOS器件中硅槽及多晶硅栅的刻蚀

ＲＭＯＳ（Ｒｅｃｔａｎｇｕｌａｒ Ｇｒｏｏｖｅｄ ＭＯＳ）器件因具有独特的性能而得到较好的应用。本文介绍用ＲＩＥ设备进行ＲＭＯＳ器件硅槽刻蚀的工艺，并对填满硅槽内的多晶硅栅的刻蚀亦作了研究。选择适当的工艺条件，可刻蚀出形貌较好的硅槽，并可在刻蚀完多晶硅后保持硅槽内多晶硅栅形貌完好 。     

用深反应离子刻蚀和介质填充技术制造具有高深宽比的超深电隔离槽

提出了一种利用深反应离子刻蚀(DRIE)和电介质填充方法来制造具有高深宽比的深电学隔离槽的新型技术.还详细讨论了DRIE刻蚀参数与深槽侧壁形状之间的关系,并作了理论上的阐述.采用经过参数优化的DRIE刻蚀深硅槽,并用反应离子刻蚀(RIE)对深槽开口形状进行修正,制造了具有理想侧壁形状的深槽,利于介质的完全填充,避免产生空洞.电隔离槽宽5μm,深92μm,侧壁上有0.5μm厚的氧化层作为电隔离材料.I-V测试结果表明该隔离结构具有很好的电绝缘特性:0～100V偏压范围内,电阻大于1011Ω,击穿电压大于100V.电隔离深槽被首次应用于体硅集成微机械陀螺仪上的微机械结构与电路之间的电气隔离与机械连接,该陀螺的性能得到了显著提高.     

基于ICP的硅高深宽比沟槽刻蚀技术

介绍了电感耦合等离子体(ICP)刻蚀技术的基本概念。结合英国STS公司的STS multiplex ICP system刻蚀机,介绍了刻蚀机原理及刻蚀过程。对硅深槽刻蚀技术进行了分析,对其中Footing效应、Lag效应和侧壁光滑问题提出了优化方案,最后在实验的基础上得出了能够刻蚀出高质量硅深沟槽的刻蚀参数。     

新型磁驱动增大检测电容的高精度MEMS惯性传感器研究

增大传感器振子的质量和静态测试电容可以减小电容式MEMS惯性传感系统的噪声,而深度粒子反应刻蚀工艺由于复杂的工艺原因,当深宽比较大时,不能刻蚀出大质量和大初始电容的传感器.据此,本文研究了一种磁驱动增大检测电容的MEMS惯性传感器,通过电磁驱动器,传感器的静态测试电容可以大幅增加,在梳齿电容上刻蚀阻尼槽后,其机械噪声达到0.61μg每根号赫兹,仿真其共振频率为598Hz,静态位移灵敏度为0.7μm每重力加速度,基于硅 玻璃键合工艺,制作了栅形条电容式惯性传感器,并用电磁驱动的方式测试其品质因子达到715,从而验证了制作工艺的可行性和电磁驱动器改变传感器初始静态测试电容的可行性.     

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

In this paper, the process and layout optimizations for improving the isolation performance of deep trench structures on SOI substrate are proposed. In the view of process flow, the reasons for forming weak points (located at the trench bottom) in deep trench structure are analyzed. In order to solve this problem of the weak points, a method of etching partial buried oxide after etching silicon is put forward, which can increase the thickness of isolation oxide at trench bottom by 10-20%. In aspect of layout structure, a voltage drop model of double trench structures is presented and verified by the experimental results, which indicates that breakdown voltage of double trench is a function of trench spacing. It is noted that the minimum trench spacing allowed by the process design rule can ensure superior isolation capability for double trench structure. Both methods for improving the performance of the device have also been verified in 0.5 μm HV SOI technology.     

Electrical properties of devices fabricated on laser-etched silicon

Focused laser etching has been investigated for use in limited area processing (LAP) of silicon wafers. The electrical properties of the etched material have been characterized for the first time by fabricating several different test structures, including isolation trenches, Schottky barrier diodes, and MOS trench capacitors. The etched material is suitable for many applications     

A novel method for etching trenches in silicon carbide

In this paper, a novel trench etching technique for silicon carbide is described. In this technique, ion implantation is used to first create an amorphous silicon carbide region. The amorphous layer is then etched away by wet chemical etching. Trenches of 0.3 to 0.8 μ have been obtained using a single implantaion/etching step. It has been demonstrated that deeper trenches can be obtained by repeating the implantation/etching step with platinum as a masking material. The etched surface was found to be smooth when compared with reactive ion etched surfaces reported for silicon carbide.     

Nearly bird's beak-free local oxidation technology for controlled dielectric formation in deep silicon trenches

Silicon deep trench isolation technology using local oxidation is reported. Scaled, high-density trench capacitors were fabricated with varying trench aspect ratios. Nearly bird's beak-free local oxidation resulted in a controlled growth of silicon dioxide on the trench bottom surfaces and significantly improved the trench gate MOS isolation characteristics. Detailed MOS capacitance measurements were performed and wafer yield in excess of 90% was demonstrated across 4 inch diameter silicon wafers.<>     

Reduction of depth variation in an Si etching process by applying an optimized run-to-run control system

A reduction of depth variation in a shallow trench isolation process is desired for obtaining more stable electrical performances of silicon devices. By applying an optimized run-to-run control system to a silicon trench etching process, trench depth variation of the process was reduced. Cp/Cpk of the trench depth of product wafers were improved from 1.10/0.83 to 1.39/1.34 by the control.     

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail.An optimized trench process is also proposed.It is found that there are two main reasons:one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect;and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom.In order to improve the isolation performance of the deep trench,two feasible ways for optimizi...     

Bulk silicon technology for complementary MESFETs

A technology for fabrication of complementary silicon MESFETs on bulk silicon substrates has been developed. The technology is similar to CMOS technology, and utilises n-silicon substrates. P-wells are used for the n-channel devices. Device isolation was achieved by trench etching. The silicides of Er and Pt were used as gate Schottky contacts. P- and n-channel characteristics are presented together with subthreshold behaviour and preliminary results regarding radiation hardness. Also, results from two-dimensional simulations of the devices are presented.<>     

双层侧壁保护的Si深槽刻蚀技术

提出了一种先进的ICP Si深槽刻蚀工艺。在"Bosch"工艺的基础上加以改进,以SF6/O2作为刻蚀气体,C4F8作为侧壁钝化气体,通过在刻蚀过程中引入少量的O2,使得在刻蚀Si深槽过程中侧壁形成由氧离子辐照产生的SiO2薄膜和CFx聚合物淀积产生的双层保护层,强烈保护Si槽侧壁不被刻蚀,保证了良好的各向异性刻蚀。同时,通过优化刻蚀和钝化的时间周期,进一步提高了刻蚀后Si槽的陡直度和平滑的侧壁效果。采用这种工艺技术可制作出满足台面晶体管、高性能梳状沟槽基区晶体管需要的无损伤、平滑陡直的Si槽侧壁形貌。     

HBr反应离子刻蚀硅深槽

对ＨＢｒ反应离子刻蚀硅和ＳｉＯ２进行了实验研究。介绍了ＨＢｒ等离子体的刻蚀特性，讨论了ＨＢｒ反应离子刻蚀硅的刻蚀机理，研究了ＨＢｒ中微量氧、碳对ＨＢｒＲＩＥ刻蚀过程的影响。实验表明，ＨＢｒ是一种刻蚀硅深槽理想的含原子溴反应气体。采用ＨＢｒＲＩＥ，可获得高选择比（对Ｓｉ／ＳｉＯ２）和良好的各向异性。