互连线和CMOS模型对性能影响的分析

在集成电路中,全局互连线的设计是关键.分析了互连线RC和RLC模型的不同特性;针对互连线与CMOS器件级联的电路进行分析.分析了集成电路中互连线和CMOS的模型对性能的影响,并给出了基于HSPICE软件的仿真结果.仿真结果表明,不同互连线和CMOS模型对系统传输特性有一定影响.     

门电路参数对互连线时延影响的仿真研究

文章推广了Wang氏RC梯形电路模型，对互连线阶跃响应上升时间与门电路参数的关系进行了仿真研究，给出了定量结果。门电路参数有输出电阻、输入电阻和电容。     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

斜阶跃信号激励下的RLC互连线时延模型

文章对斜阶跃信号激励下的RLC互连线时延模型进行了研究.用改进1阶模型逼近传输线的传输函数,得到了比较简洁的时延解析式.该模型计算所得的结果与SPICE仿真结果的误差小于5%.     

基于RLC模型的树形互连线时延估算

文章给出了基于RLC模型的树形互连线50％时延的估算公式。这里给出的算法精度较高(与SPICE仿真结果的误差在10％以内)，而且具有与Elmore时延相同的算法复杂度。该算法基于RLC模型，可以得到各种不同的阻尼响应，包括欠阻尼振荡，而Elmore时延只能反应呈单调变化的过阻尼响应。因此，该算法对阻尼响应的估算精度高于Elmore时延，而其相当的计算开销(算法复杂度)使它可以应用于Elmore时延使用的各个领域。     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

电容充电电路的能量效率分析

本文结合RC电路和RLC串联电路,讨论了电容充电电路的能量效率。对RC电路,分析了采用指数型电压源进行充电的能量效率。对RLC串联电路,讨论了各种响应特性下进行充电的能量效率,并指出如果利用电路的欠阻尼响应特性,可以大幅提高充电的能量效率。本文的讨论对“电路”课程的教学具有一定的参考价值。     

无损线终端接任意负载暂态响应分析

本文基于均匀线方程,利用拉普拉斯变换,研究了阶跃激励在终端和起端都不匹配的无损均匀线上多次反射传输情形,借助负载中储能元件响应产生过程的"附加电源",推导出终端为任意负载时求解暂态响应的一般方法,最后通过RC电路和RLC电路分析及仿真实验加以验证了该求解方法的正确性.     

分布RLC树形互连线的时延估算稳定模型

基于分布RLC互连线模型,提出一种保证结果稳定的树形互连线的时延估算模型.此模型针对树形互连线,提出"等效ABCD矩阵"的概念,在此基础上通过二阶矩匹配估算树形互连线时域响应,并通过曲线拟合给出了解析形式的50%时延估算公式.新模型保证结果的稳定性,并且大大快于传统的仿真方法.实验表明,新模型与电路仿真软件HSPICE仿真结果相比较误差小于15%.     

DSM interconnects: importance of inductance effects and corresponding range of length

To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-/spl mu/m technology.     

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion

/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.     

Figures of merit to characterize the importance of on-chipinductance

A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-μm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Some observations concerning the methods of filter/oscillator realization using the concept of FDNR

It has been shown that the method of converting a passive RLC low-pass (LP) filter into an inductorless filter using the concept of frequency-dependent negative resistance (FDNR) is equivalent to first applying the low-pass-to-high-pass (LP → HP) transformation and then the RC:CR transformation on the LP filter. Also, the RLC model of an active-RC oscilator and the corresponding RCD model derived from this through Bruton's transformation are RC:CR transforms of each other. The latter observation suggests that many novel oscillator circuits can be generated from existing ones through RC:CR transformation.     

IC封装中互连线信号完整性的研究

随着电子芯片向着高密度、高频率和小体积化方向发展,IC封装的结构尺寸及其互连线系统在信号完整性、损耗等多方面影响着整个电路系统的可靠性。因此,对IC封装及其互连线电特性的分析显得尤为重要。文章以四列直插芯片封装外壳模型为设计实例,利用AnsoftQ3D软件提取了该封装模型的寄生电阻、电容和电感（RCL）,并结合Mult...     

Switch-factor based loop RLC modeling for efficient timing analysis

Timing uncertainty caused by inductive and capacitive coupling is one of the major bottlenecks in timing analysis. In this paper, we propose an effective loop RLC modeling technique to efficiently decouple lines with both inductive and capacitive coupling. We generalize the RLC decoupling problem based on the theory of distributed RLC lines and a switch-factor, which is the voltage ratio between two nets. This switch-factor is also known as the Miller factor, and is widely used to model capacitive coupling. The proposed modeling technique can be directly applied to partial RLC netlists extracted using existing parasitic extraction tools without advance knowledge of the return path. The new model captures the impact of neighboring switching activity as it significantly affects the current return path. As demonstrated in our experiments, the new model accurately predicts both upper and lower delay bounds as a function of neighboring switching patterns. Therefore, this approach can be easily implemented into existing timing analysis flows such as max-timing and min-timing analysis. Finally, we apply the new modeling approach to a range of activities across the design process including timing optimization, static timing analysis, high frequency clock design, and data-bus wire planning.     

Closed-Form RC and RLC Delay Models Considering Input Rise Time

The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmore's approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy.     

一种基于RLC元包的有损传输线的渐近式构造模型

通过引入两个RLC元包,本文提出了一种针对有损传输线驱动点导纳的 γ d n 模型构造方法,只要有规律地增加RLC元包的个数,该模型很容易实现高阶扩展以适应工作频率和模型精度的要求,并保持等效后电路的稳定性和无源性.SPICE仿真结果表明该模型要比通常使用的开端等效 p 模型具有更高的精度.