面向工程化教育的有限状态机教学设计

有限状态机是"硬件描述语言"课程教学的重点和难点。本文深入分析当前有限状态机教学的现状,指出有限状态机教学与工程化人才培养需求的之间差距。在此基础上,论文提出并阐述了一种问题驱动的有限状态机教学体系,对算法状态机图和模板式编码风格等有限状态机设计的相关概念和方法进行了阐述。     

应用遗传算法进行低功耗状态编码

本文研究了用遗传算法进行有限状态机(FSM)的低功耗状态编码问题.基于FSM的概率模型,对编码空间进行并行搜索;通过在适应性度量中引入面积和状态翻转信息,实现了面积和功耗之间的折衷.对一些FSM的实际测试表明此方法平均能达到20%的功耗优化.     

在FPGA中状态机的编码方式

在FPGA(现场可编程门阵列)器件设计中,状态机的设计方法是最常用的设计方法之一,而通过怎样的编码形式才能达到最好的设计要求,成为设计所要解决的一个很重要的问题.在状态机的编码方式中,最常用的是顺序编码和One-hot编码方式.文中通过对这两种状态机编码方式的优缺点比较,说明应该如何选择编码方式,以及如何避免在此过程中可能出现的一些错误.     

基于Verilog HDL的可综合有限状态机设计

Verilog HDL(硬件描述语言)不仅可以在门级和寄存器传输级进行硬件描述,也可以在算法级对硬件加以描述。有限状态机是数字系统中的重要组成部分。文中研究了用Verilog HDL设计有限状态机时可以采用的不同的编码方式和描述风格,并介绍了有限状态机综合的一般原则。最后以存储控制器状态机为例,分别用Synplify Pro和QuartusⅡ对设计进行了综合和仿真验证。     

Reliability Strategies for Data Transmission in Wireless Mesh Network

Wireless Mesh Network (WMN) is a new-type wireless network. Its core idea is that any of its wireless equipment can act as both an Access Point (AP) and a router. Each node in the network can send and receive signals as well as directly communicate with one or several peer nodes. One important issue to be considered in wireless Mesh networks is how to secure reliable data transmission in multi-hop links. To solve the problem, the 3GPP system architecture proposes two functionalities: ARQ and HARQ. This paper presents two HARQ schemes, namely hop-by-hop and edge-to-edge, and three ARQ schemes: hop-by-hop, edge-to-edge, and last-hop. Moreover, it proposes three solutions for WMNs from the perspective of protocol stock design: layered cooperative mechanism, relay ARQ mechanism and multi-hop mechanism.     

基于SUPL状态机的AGPS终端的软件实现

抽象语法标记(ASN.1)广泛应用于数据通信领域.AGPS技术中的SUPL协议即采用了ASN.1中的压缩编码规则(PER)进行消息、数据的编解码.文章分析了SUPL协议中各种消息及数据的ASN.1描述和PER编码规则接口,并在此基础上介绍了一种基于PDA操作系统平台,以状态机为核心的SUPL协议客户端的软件实现.     

Smartphones to Account for 2/3 of World＇s Mobile Market by 2020, Says New GSMA Intelligence Study

11 September 2014,Hong Kong:Smartphones will account for two out of every three mobile connections globally by 2020,according to a major new report by GSMA Intelligence,the research arm of the GSMA.The new study,"Smartphone forecasts and assumptions,2007-2020",finds that smartphones account for one in three mobile connections today,representing more than two billion mobile connections.It forecasts that the number of smartphone connections will grow three-fold over the next six years,reaching six billion by 2020,accounting for two-thirds of     

数字电路倍增设备低速率语音编码方案的选择

新一代数字电路倍增设备(DCME)中将采用更低速率的语音编码技术.文中介绍了几种ITU-T公布的低速率语音编码技术,对其时延、编码质量以及算法复杂度等进行了比较,最后就DCME的不同应用场合选择了适合的语音编码方案.     

Optical fiber sensor by cascading long period fiber grating with FBG for double parameters measurement

An optical fiber sensor for strain and temperature measurement based on long period fiber grating (LPFG) cascaded with fiber Bragg grating (FBG) structure has been proposed and realized both theoretically and experimentally. Theoretical analysis shows that two microstructures with similar sensitivities cannot be used for double parameters measurement. The LPFG is micromachined by the CO2 laser, and the FBG is micromachined by the excimer laser. For the validation and comparison, two FBGs and one LPFG are cascaded with three transmission valleys, namely FBG1 valley at 1 536.3 nm, LPFG valley at 1 551.2 nm, and FBG2 valley at 1 577.3 nm. The temperature and strain characteristics of the proposed sensor are measured at 45—70 °C and 250—500 με, respectively. The sensitivity matrix is determined by analyzing wavelength shifts and parameter response characterization of three different dips. The proposed optical fiber sensor based on LPFG cascaded with FBG structure can be efficiently used for double parameters measurement with promising application prospect and great research reference value.     

并行行旁路乘法器的设计与实现

为了进一步降低乘法器运算过程中的延迟,减少功耗,在行旁路乘法器的基础上进一步优化,提出一种并行行旁路(PRB)乘法器,并用有限状态机进行了实现.在行旁路的基础上,通过对乘数进行重新编码并行输出部分积,使乘法运算中产生的部分积数量减少,提高运算速度;利用有限状态机实现PRB乘法器,有效减少了电路中逻辑元件的数量,降低了功耗.在Quartus平台上进行的仿真表明PRB乘法器在整体性能上有较大的改善.     

Partitioned state encoding for low power in FPGAs

The problem of finite state machine (FSM) encoding for low power in field-programmable gate arrays (FPGAs) is addressed. In this technology, one-hot encoding is typically recommended for large FSMs and binary encoding for small FSMs. A partitioned encoding approach is proposed which uses a combination of both binary encoding and zero-one-hot encoding with intermediate code size. Experimental results demonstrate that the proposed encoding approach can produce significant power savings.     

非规则LDPC码编码器的FPGA实现

文中硬件实现了一种非规则的低密度奇偶校验码在一定的约束条件下,利用具有一定结构的校验矩阵来降低编码复杂度的LDPC码,并给出了编码器设计实现原理、结构和基本组成。在Quartus 9.0软件平台上采用基于FPGA的Verilog硬件描述语言,在Altera的Cyclone系列型号为EP1C6Q240C8N的芯片硬件平台实现了整个编码过程中所有模块的功能,并通过Matlab验证了编码结果的正确性。同时,该编码方案还可灵活应用于不同码长的系统中。     

Implementation of finite-state machines based on programmable logic ICs with the help of the merged model of Mealy and Moore machines

The problem concerning the synthesis of finite-state machines (FSMs) based on programmable logic ICs, in which FSM’s output variables serve as the code (or part of the code) of internal states, has been examined. A solution to the problem is obtained with the help of the merged model of Mealy and Moore machines. A principal distinction between the proposed and well-known techniques is that an initial FSM undergoes no conversions related to an increase in the number of internal states and transitions thereof. The necessary conditions under which output variables can be used as the code of FSM’s internal states are presented. The method for synthesizing the merged model AC of Mealy and Moore machines is described. Basic results of investigations, as well as promising directions of further studies concerned with the development of new structural models of FSMs, are discussed.     

基于FPGA的卷积码译码器设计

针对目前卷积码译码器占用资源较多,最高工作频率较低的缺点,设计了基于FPGA的（2,1,8）卷积码译码器。该译码器采用硬判决维特比译码算法。为有效提高译码器的工作频率,采用寄存器存储路径度量和幸存路径。通过分析译码启动过程中状态转移图上各个状态与其前一状态的关系,找到了硬件实现该过程的一种简单方法。通过分析译码过程中各个状态路径度量值之间的差值的变化规律,找到了采用硬判决维特比译码算法时,存储各个状态路径度量值的寄存器的最小位宽。在Quartus2集成开发平台上用Verilog HDL语言编写了译码器的源代码,并进行了编译、综合、仿真。结果表明所设计的卷积码译码器工作频率高,且输出时延小,占用资源较少。具有一定的实用价值。     

基于FPGA的RS编码器的设计与实现

RS码是线性分组码中一种典型的纠错码,既能纠正随机错误,也能纠正突发错误.在现代通信领域越来越受到重视.文中介绍基于FleA使用Verilog-HDL语言的RS(15,9)编码器的设计方法,并在QuartusII 5.0软件环境下进行了功能仿真,仿真结果与理论分析相一致,该设计方法对实现任意长度的RS编码有重要参考价值.     

Turbo编码和交织器研究的新进展

Turbo码自提出以来一直是世界范围内信息与编码界的热点，短短十年来Turdo码的发展经历了由仿真分析到理论探讨再到实践应用的不断发展的过程。主要介绍了近三年来Turdo码编码和交织器研究的新进展。     

利用FPGA实现HDB3编解码功能

HDB3（三阶高密度双极性）码具有无直流分量、低频成分少、连零个数不超过3个、便于提取时钟信号等特点。通过对HDB3编解码原理进行分析和研究,提出一种基于FPGA的HDB3编解码实现方法,给出VerilogHDL语言的实现方法和仿真波彤,完成硬件电路的设计和测试,采用该方法设计的HDB3编解码器已应用于相关实验设备中。     

有限状态机的Verilog设计与研究

本文研究了用Verilog实现有限状态机的各种不同的编码方式和描述风格，并从综合，毛刺，面积，速度这几方面研究了不同实现方式的利弊。最后，以SoC芯片中DMA Arbitor有限状态机为例，我们用Design Complier（DC）对七种设计进行了综合，并分析了综合后的面积和时延信息。     

Circuit Level Concurrent Error Detection in FSMs

Finite state machines (FSMs) are contained in many building blocks of digital electronic circuits. Such electronic circuits are prone to transient errors, caused e.g. by cosmic radiation, and to permanent errors. In this article, the authors give an overview of known error detection methods for FSMs. One method (dependent state encoding for dynamic error detection) is described in detail, as well as the problems arising when the method is applied to a practical example. Additionally, the authors propose a modification of the method above. For several benchmark circuits, this modification shows better results, compared to the state-of-the-art implementation.     

基于FPGA的CMI编码系统设计

提出了一种基于FPGA并利用Verilog HDL实现的CMI编码设计方法.研究了CMI码型的编码特点,提出了利用Altera公司Cyclone Ⅱ系列EP2C5Q型号FPGA完成CMI编码功能的方案.在系统程序设计中,首先产生m序列,然后程序再对m序列进行CMI码型变换.在CMI码型变换过程中,采用专用寄存器对1码的...