一种快速伪码捕获算法

在扩频通信系统中,伪码捕获跟踪是通信的基础,捕获时间的长短直接影响系统性能。为缩短捕获时间,可以采用并行、FFT频域捕获等方法。介绍了一种采用Walsh变换进行伪码捕获的方法,整个过程只需一次Walsh运算,可以进一步缩短捕获时间,并且只涉及加法而没有FFT运算所需的复数和乘法运算,具有运算速度快、占用资源少、实现简单等特点。     

FDM调制解调中高速（I）FFT硬件设计

提出了一种64点，512点和1024点（I）FFT（（逆）快速傅里叶变换）的硬件实现方法，适合应用在正交频分复用（OFDM）系统中，实现时采用了16位精度的复数来表示输入输出数据。该算法在运算过程去除了所有的乘法器在运算过程中没有使用乘法器，使得运算速度得到较大地提高。     

一种实序列FFT新算法与C语言实现

实际中需做快速傅里叶变换(FFT)的多为实序列数据,而其变换算法都是以复数序列作为输入。文中利用频域的性质,将实序列数据变换为复数序列,再进行FFT变换,以提高FFT对于实序列输入的变换效率,最后用C语言实现该算法并与传统算法进行实验对比,从结果可看到优化后效率提高很多。     

二维级联流水结构大点数FFT运算器实现研究

大点数快速傅里叶变换(FFT)运算在雷达、通信信号侦察中有广泛应用,其基于现场可编程门阵列(FPGA)的实现方法有重要的研究价值。推导出点数为N的大点数FFT运算分解为2级小点数FFT运算级联的运算公式,在此基础上给出其实现步骤,从流水线结构设计、基本运算单元以及地址生成等方面详细介绍一维列(行)变换的工程实现方法,并给出列、行变换之间所乘旋转因子的压缩算法。工程实际应用表明,该大点数FFT运算器具有变换速度快、调试方便及可在单片FPGA实现的优点。     

高基数快速傅里叶变换的实现

提高实现的并行性和实时性是目前FFT(快速傅里叶变换)研究的一个重点。介绍了在CPLD(复杂可编程逻辑器件)中实现高基数FFT的一种方法。以较低基数的FFT搭建高基数的FFT,大大提高了变换的速度。文中以基16 FFT的实现为例,介绍了以基2实现基16运算的过程,着重描述了运算核的设计以及数据的存储和调用。     

应用于FFT处理器的新型串接CSD常数乘法器设计

快速傅里叶变换(FFT)广泛应用于正交频分复用(OFDM)系统的调制与解调中。FFT的输出需要输入序列与旋转因子(TF)进行复数乘法运算,由于正则有符号数(CSD)常数乘法器实现简单、硬件开销小,常用于此类复数乘法运算,但随着旋转因子常数值个数的增加,其硬件开销会成倍增长。为了降低硬件开销,利用参数分解减少常数值个数的方法,提出了一种新型串接CSD常数乘法器。仿真结果显示对比常用的布斯乘法器,该新型串接CSD常数乘法器设计方案实现与旋转因子Wi128、Wi256以及Wi512进行复数乘法运算的硬件资源消耗分别减少41%、34%和25%。     

快速傅氏变换的一个改进算法

正 我们知道,对于N=2点的复数离散序列,快速算法能以(N/2)次复数乘法实现其傅氏变换,比N2次复数乘法的实现方法,运算次数大为减少,速度大为提高。这对数值计算和数字信号处理技术都有重大的意义。快速傅氏变换(FFT)出现虽仅有15年,但已有了很大的发展,在实践中已得到广     

基于CORDIC旋转器的基-3 FFT算法高效设计

设计出一种可以用于FPGA高效实现的基-3 FFT算法,采用改进的三端前馈延迟转换器结构,优化了延迟和运算过程。针对蝶形运算中复数乘法器占据大量内存的问题,引入了CORDIC旋转器实现输入与旋转因子相乘的运算,可以降低乘法运算的复杂度,该CORDIC旋转器采用改进的高基CORDIC算法,解决了传统的CORDIC算法迭代次数多、延迟大的问题,从而达到高吞吐率要求。该基-3 FFT算法以寻址变序、流水处理的方式,可以满足最高运行频率为404 MHz的FFT处理要求。与基于传统复数乘法器的基-3 FFT算法相比,基于CORDIC旋转器的基-3 FFT算法使功耗平均减少了22%,使总延迟平均减少了29%。     

基于FPGA的激光测距系统中基4算法的FFT研究

文章提出了利用可编程逻辑器件FPGA通过硬件来实现快速傅立叶变换( FFT)的基4 算法,提出了采用两个蝶形运算器同时并行计算,每次蝶形运算按顺序进行的结构,将并行处理与顺序处理相结合,提高并行度和数据吞吐量,每次蝶形运算时间不超过1μs,完成整个256点复数FFT运算大约需要120μs左右,同时又节省资源。该方法在激光矿井提升机位置跟踪系统中应用取得了良好效果。     

FDM调制解调中高速(Ⅰ)FFT硬件设计

提出了一种64点,512点和1024点(Ⅰ)FFT((逆)快速傅里叶变换)的硬件实现方法,适合应用在正交频分复用(OFDM)系统中,实现时采用了16位精度的复数来表示输入输出数据.该算法在运算过程去除了所有的乘法器在运算过程中没有使用乘法器,使得运算速度得到较大地提高.     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements     

VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers

The problem of an efficient very large scale integration (VLSI) realization of the direct/inverse fast Fourier transform (FFT/IFFT) for digital subscriber line (DSL) applications is addressed in this paper. The design of scalable and very high-rate (VDSL) modem claims for large and high-throughput complex FFT computations while for massive and fast deployment of the xDSL family low-cost and low-power constraints are key issues. Throughout the paper we explore the design space at different levels (algorithm, arithmetic accuracy, architecture, technology) to achieve the best trade-off between processing performance, hardware complexity and power consumption. A programmable VLSI processor based on a FFT/IFFT cascade architecture plus pre/post-processing stages is discussed and characterized from the high-level choices down to the gate-level synthesis. Furthermore low-power design techniques, based on clock gating and data driven switching activity reduction, are used to decrease the power consumption exploiting the correlation of the FFT/IFFT coefficients and the statistics of the input signals. To this aim both frequency-division and time-division duplex schemes have been considered. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Synthesis results for a 0.18 μm CMOS standard-cells technology show that the processor is suitable for real-time modulation and demodulation in scalable full-rate VDSL modem (64-4096 complex FFT, 20 Msample/s) with a power consumption of few tens of mW. These performances are very interesting when compared to state-of-the-art software implementations and custom VLSI ones.     

Hartley变换OFDM调制的可见光通信研究

针对正交频分复用(OFDM)可见光通信系统中存在高峰均功率比的问题，将预编码与迭代限幅滤波技术相结合应用于Hartley变换OFDM调制的可见光通信系统中，并对传统的采用FFT/IFFT限幅滤波的OFDM系统进行改进。根据建立的FHT的可见光OFDM系统模型，分别比较了不同方案下系统的频谱利用率、PAPR和误码率等性能，并分析了离散余弦变换和Hadamard矩阵预编码对PAPR的抑制作用以及FFT/IFFT、DCT/IDCT和FHT/IFHT三种不同变换方案的滤波性能。结果表明:FHT的可见光OFDM系统比FFT的OFDM系统的计算复杂度低、频谱利用率高；DCT预编码技术在克服系统PAPR及提升系统误码性能上更具优势；FHT/IFHT迭代限幅滤波的误码性能优于FFT/IFFT和DCT/IDCT。      

数模同播音频广播系统中OFDM调制解调器的设计

设计了一种基于IFFT/FFT的高效OFDM调制解调器,实现数模同播音频广播系统中数字音频信号的OFDM调制解调,包括发射机中用于形成OFDM符号的时域与频域交织模块、OFDM调制模块和接收机中OFDM解调模块、时域与频域解交织模块。通过对IFFT/FFT算法的改进,该OFDM调制解调器中数据的输入顺序和输出顺序相同,不需要进行顺序输人逆序输出,并且可以把现有基2的幂次方的FFT变换扩展到任意点,实现适用于任意点的IFT/FFT,简化了IFFT/FFT模块本身和交织／解交织的资源消耗,巧妙地节省了系统所需的资源。     

一种频率步进雷达目标运动参数估计方法

为实现低信噪比下目标的精确运动补偿,提出基于Keystone变换和Morlet小波变换的方法估计低信噪比下目标速度和初始距离参数。在分析频率步进雷达运动目标回波信号基础上,首先采用Keystone变换法去除回波信号高次相位项,然后对回波信号做IFFT运算,再进行FFT 操作,便可得到距离-速度二维参数谱。考虑低信噪比对参数估计的影响,文中将距离维参数谱通过Morlet小波变换去除噪声,进而获得目标运动参数的精确估计。最后计算机仿真实验进一步说明了该方法的有效性。     

An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n

A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1–4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um CMOS technology and saves 25% area compared to a conventional implementation approach using radix-2³ algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length; it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN standard.

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

基于DSP的正交频分复用的实现

在理论上推导了采用快速傅里叶逆变换/傅里叶变换(IFFT/FFT)实现正交频分复用(OFDM)调制解调的可行性,分析了采用IFFT/FFT实现OFDM调制解调比传统方法更具优势;然后在数字信号处理器(DSP)硬件平台上对采用IFFT/FFT实现OFDM调制解调进行了验证。实验结果表明:采用IFFT/FFT不仅能正确实现OFDM信号的调制解调,而且还大大简化了OFDM系统结构,降低了系统实现难度,节约了成本。     

快速傅立叶变换辅助设计数字低通滤波器

详尽讨论了快速傅立叶变换(FFT)应用于有限冲击响应(FIR)数字低通滤波器(DLPF)的设计和分析方法.应用FFT算法,将理想DLPF幅频特性转换到变换域,获得其变换域序列;设计窗函数对该序列开窗,获得FIR有限序列;应用快速傅立叶逆变换(IFFT)对其进行变换,获得相应窗函数可实现DLPF幅频特性.结果发现,FFT算法可获得与传统卷积算法相同的结果;不需要推算窗函数的频谱解析表达式;可以处理Kaiser窗等变换域解析式复杂、频域解析式难以精确求解的窗函数设计与分析.与传统的卷积分析法相比,FFT不仅算法简单、灵活,而且处理能力强,是分析FIR DLPF设计的有力工具.     

基于802.11a的FFT/IFFT处理器设计

设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.