A micropower class-AB CMOS log-domain filter for DECT applications

This paper presents a micropower second-order low-pass filter using the log-domain principle and integrated in a 0.35-μm CMOS process. It has been designed as an antialiasing filter for a DECT transceiver with a 45-kHz nominal cutoff frequency. The circuit uses transistors biased in weak inversion without requiring separate wells. It operates at 1.5-V supply voltage and its current consumption is 8 μA in idle mode. The log-domain filter is implemented with an on-chip conditioner which allows class-AB operation. It can process input currents at 5 kHz that are 25 times larger than the 200-nA bias current. Measurements up to 500 times the bias current have been done, since at 1 kHz the input current is only limited by the supply voltage     

A low-distortion BiCMOS seventh-order Bessel filter operating at2.5 V supply

This paper presents the design of a seventh-order continuous-time Bessel filter using a new low-voltage and highly linear BiCMOS transconductor. A high-gain and parasitic-insensitive integrator is obtained by using an active capacitor scheme. The filter has been designed to operate at a 2.5 V supply with a nominal -3 dB cutoff frequency of 600 kHz. It has been fabricated in 1 μm, double-poly 6-GHz BiCMOS process. The inband group delay variation is less than 10 ns. The total harmonic distortion (THD) measured with a 100 kHz input signal is less than -49 dB for a 2 V_pp amplitude and the dynamic range is 77 dB. The filter can be frequency tuned over almost one decade with a gain variation less than 0.2 dB in the passband. A common-mode rejection ratio (CMRR) of 53 dB in the passband is observed, thanks to a careful common-mode control strategy     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

1.2-V 5-/spl mu/W class-AB CMOS log-domain integrator with multidecade tuning

An integrator employing the log-domain principle and fabricated in a 0.8-/spl mu/m CMOS process is presented. It uses floating-gate MOS transistors biased in weak inversion to achieve low-voltage operation and low power consumption. The circuit does not suffer from initial charge trapped in the floating gates, thus not requiring postfabrication charge removal. It can be frequency tuned over more than three decades, from 25 Hz to 35 kHz, and uses a 1.2-V single supply to achieve a dynamic range at 1% THD of 75 dB thanks to its balanced class-AB operation. For cutoff frequencies in the range of 100 Hz, the supply voltage can be reduced down to 1 V. The circuit occupies an active area of 0.1 mm/sup 2/ and dissipates 4.7 /spl mu/W. The technique employed can be readily extended to high-order filters.     

Low-power current-mode 0.9-V voltage regulator

A design for a low-power integrated 0.9-V voltage regulator for load currents up to 140 μA is presented. The circuit contains no external components and it stabilizes the voltage of a single battery cell of 1.1-1.6 V with a PSRR >40 dB over a frequency range of up to 30 kHz. The regulating circuit operates a current level and accomplishes automatic load-current limiting. Its r.m.s output noise is <4 μV over a frequency range of 10 Hz-8 kHz. The quiescent supply current is ≈40 μA     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a1-Vp-p range

This paper describes the design and measured results of an all-n-p-n low-voltage (2.5 V), low-current (1 mA), large-swing (1 V_p-p), low-distortion (-53 dB, 1 V_p-p) active filter using a conventional bipolar process. The transconductors for the filter are composed of Gilbert cell transconductors. Distortion has been improved by feedback circuits without increasing the supply voltage and without using p-n-p transistors. The filter is a gyrator-capacitor type third-order Butterworth low-pass filter with a nominal cutoff frequency of 192 kHz. A voltage scaling technique has been applied directly to the gyrator-capacitor filter. This has improved the signal-to-noise ratio by 3 dB. Simulation results indicated that a fast operation up to tens of MHz is possible with a standard bipolar process, as the signal path is composed only of n-p-n transistors     

A New Current-Mode Synthesis Method for Dynamic Translinear Filters and its Applications in Hearing Instruments

A new current mode synthesis method for dynamic translinear filters is proposed. As a design example, we have considered an ultra-low power second order filter working in audio frequency range, for hearing aids application, and using subthreshold MOS devices. It has a nominal supply voltage of 1.2 V and works down to 1 Volt. It has a power consumption of 5 W. The filter cut-off frequency and its Q factor can be tuned respectively from 600 Hz to 13 kHz and from 0.6 to 1.1. Mismatch problems are investigated on the circuit level and an on-chip compensation method is proposed.     

全差分可调频率四阶Chebyshev滤波器的实现

提出了一种新的全差分运算放大器,该运算放大器在具有电压共模负反馈的同时还具有电流共模负反馈,能较好地稳定其工作点。通过利用MOS管工作在线性区便能作可变电阻之用的特性,设计实现了基于R-MOSFET-C运放的全差分频率连续调节的四阶Chebyshev低通滤波器。该滤波器采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)5V电源电压、0.5m CMOS工艺生产制造。其芯片面积大小为0.36mm~2,截止频率调节范围为20kHz到420kHz,输入信号频率在100kHz,2.5Vpp时的失真小于-65dB,功耗仅为16mW。     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

A low-voltage ultra-low-power translinear integrator for audiofilter applications

In this paper, the design and measurement of a l-V translinear integrator and its application in a controllable second-order lowpass filter for hearing instruments is presented. A semicustom version of the filter has been integrated in a standard 2-μm, 7-GHz, bipolar IC process and operates at voltages down to 1 V, consumes only 6 μA, and has a dynamic range of 57 dB for a total harmonic distortion below 2%. Its cutoff frequency is linearly adjustable in octaves from 1.6 to 8 kHz     

`R-lens filter': An (RC)n current-mode lowpass filter

A continuous-time (RC)ⁿ lowpass filter is presented that can be fully integrated with cutoff frequency down to the 0.1 MHz range. The circuit is based on a cascade of new compact RC-cells that provides current amplification and filtering with minimum power dissipation (<15 μW/pole) using a single supply voltage (2 V). The high value resistance of the RC-cell is obtained by means of a current conveyor feedback that de-magnifies the signal current flowing in a small physical resistor. The circuit is intrinsically low-noise due to a `cooling effect' in the equivalent resistor     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138 kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3 V power supply and 0.35 μm CMOS technology. Chip test results demonstrate better than −68 dB THD with 70 kHz, 2.0V_pp signal, frequency turning range of more than 14,000 from 3 Hz to 420 kHz, chip area of 0.36 mm² and power consumption of 16 mW.     

A 20-Hz-to-200-kHz magnetic flux probe for EMI surveys

A small magnetic flux probe is described. It exhibits a magnetometer-like response over the frequency range of 20 Hz to 200 kHz with an effective antenna height of 1 m. The E-field equivalent noise floor of this device is ~10 μV/m√Hz at 10 kHz. A switchable high-pass filter is included to allow the measurement of very low frequency fields in the presence of strong 50-400-Hz power-line fields. The distinguishing features of this probe are its method of winding and shielding. Both the theory of operation and practical construction are described     

Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC'sin 3.3 V CMOS technology

A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 μm CMOS process. The regulator is able to deliver peak current transients of 300 mA, while the output voltage remains within a margin of 10% around the nominal value. The circuit draw's a static quiescent current of 750 μA during normal operation, and includes a power-down mode with only 10 μA current consumption. The die area is 1 mm², and can be scaled proportional to the maximum peak current. Special precautions have been taken to allow 5 V in the 3.3 V process     

A fully integrated neural recording amplifier with DC input stabilization

This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes.     

Multimode $G_{m}$– $C$ Channel Selection Filter for Mobile Applications in 1-V Supply Voltage

A CMOS transconductor for multimode channel selection filter is presented. The transconductor includes a voltage-to-current converter and a current multiplier. Voltage-to-current conversion employs linear region MOS transistors, and the conversion features high linearity over a wide input swing range. The current multiplier which operates in the weak inversion region provides a wide transconductance tuning range without degrading the linearity. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18 mum CMOS process. The measurement results show that the filter can operate with the cutoff frequency of 135 kHz to 2.2 MHz. The tuning range and the linearity performance would be suitable for the wireless specifications of GSM, Bluetooth, cdma2000, and wide-band CDMA. In the design, the maximum power consumption at the highest cutoff frequency is 2 mW under a 1-V supply voltage.     

GaAs switched capacitor DC-to-DC converter

A switched capacitor DC-to-DC negative converter fabricated in GaAs MESFET technology is introduced in this paper. The converter has an oscillator that runs at 250 kHz, and requires two external capacitors, 0.1 and 1 μF. The converter runs off a wide range of supply voltage, 2 to 10 V, and has a typical output impedance of 75 Ω. A typical open circuit voltage conversion efficiency of 99.6% is achieved. The circuit can be integrated with other GaAs circuits to provide an on-chip negative supply. Measured, simulated and analytical results are introduced in this paper