采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

三值双传输管电路的通用综合方法

提出采用双传管逻辑设计三值电路的方法,对每个MOS管的逻辑功能均采用传输运算予以表示以实现有效综合.建立了三值双传输管电路的反演法则和对偶法则.新提出的三值双传输管逻辑电路具有完全基于标准CMOS工艺,无需对MOS管作任何阈值调整,结构简单、规则,输入信号负载对称性好,逻辑摆幅完整以及无直流功耗等特点.采用TSMC 0.25μm工艺参数和最高电压为3V的HSPICE模拟结果验证了所提出综合方法的正确性.     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

Clocked CMOS adiabatic logic with integrated single-phasepower-clock supply

The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 μm CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary     

A 3.8-ns CMOS 16×16-b multiplier using complementarypass-transistor logic

A 3.8-ns, 257-mW, 16×16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K     

True single-phase adiabatic circuitry

Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 μm standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts     

Modelling the operation of pass transistor and CPL gates

Pass transistor logic and complementary pass-transistor logic (CPL) are becoming increasingly important in the design of a specific class of digital integrated circuits owing to their speed and power efficiency as compared with conventional CMOS logic. In this paper, a simple and very accurate technique for the timing analysis of gates that involve pass transistor logic is presented. This investigation offers for the first time the possibility of simulating pass transistor and CPL gates by partitioning the behaviour of complex structures into well defined subcircuits whose interaction is studied separately. Using the proposed analysis, which is validated by results for two submicron technologies, most pass-transistor logic styles can be modelled efficiently. Consequently, a significant speed advantage can be gained compared with simulation tools that employ numerical methods such as SPICE.     

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.     

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25-μm CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V     

Four-phase improved adiabatic pseudo-domino logic

A four-phase improved adiabatic pseudo-domino logic family is presented. The proposed logic family, IAPDL-4φ, is an extension of IAPDL (improved adiabatic pseudo-domino logic). It has the same circuit structure as IAPDL, but a different clocking system is applied. A four-phase clock-supply to facilitate pipelining of the design is used in addition to a reduced pulsewidth for the auxiliary clocks. As a result, the speed is improved by about a factor of two, and power dissipation is decreased by ~65% for various shift registers at 200 MHz, compared to IAPDL     

Noncomplementary BiCMOS logic and CMOS logic for low-voltage,low-power operation-a comparative study

This paper presents results of a comprehensive comparative study of six bipolar complementary metal-oxide-semiconductor (BiCMOS) noncomplementary logic design styles and two CMOS logic styles for low-voltage, low-power operation. These logic styles have been compared for switching power consumption and power efficiency (power-delay product). The examination offers two alternative approaches never used in other comparative studies. First, all BiCMOS-based styles are compared to low-power CMOS styles as opposed to a single conventional static CMOS style. Second, a low-power methodology has been used as opposed to performance methodology referred to in the previous logic comparisons. The styles examined are bootstrapped BiCMOS, bootstrapped full-swing BiCMOS, bootstrapped bipolar CMOS, Seng-Rofail's bootstrapped BiCMOS, modified full-swing BiCMOS, dynamic full-swing BiCMOS, double pass-transistor CMOS, and inverter-based CMOS. These design styles have been compared at various power supply voltages (0.9-3 V), with various output load capacitances (0.1-1 pF) at the frequency 50 MHz and temperature 27°C. The results clearly show which logic style is the most beneficial for which specific conditions     

Top-down pass-transistor logic design

The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called “circuit inventor” is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed     

Design and implementation of differential cascode voltage switchwith pass-gate (DCVSPG) logic for high-performance digital systems

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type of ratioless circuit, and it also provides superior performance with less power dissipation and better silicon area tradeoff. The basic DCVSPG design technique, the methodology for optimization, and synthesis of the pass-gate logic tree are described. The standard cell library development taking advantage of the dual-rail outputs of DCVSPG gates is also discussed. The performance comparisons with other existing pass-gate circuit techniques [complimentary pass-transistor logic (CPL), double pass-transistor logic (DPL), and swing restored pass-transistor logic (SRPL)] are presented. For more robust design, the DCVSPG with inverter buffers is also the best choice. A Viterbi macro design using the DCVSPG circuit technique is demonstrated. The process that the design is based upon is a 0.5-μm CMOS technology with 0.25-μm effective channel length and five layers of metal. This macro can run up to 500 MHz at the nominal process condition. In comparison with other existing dynamic circuit techniques, the results also clearly show that the dynamic DCVSPG has the superior power-delay performance     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz     

VLSI compressor design with applications to digital neural networks

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. In this paper, such a compressor design based on complex complementary pass-transistor logic (C²PL) is presented. Some types of 3-2 compressors in C²PL are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the C²PL compressors have the best performance in power, delay and number of transistors     

采用三相交流电源的低功耗绝热时序电路

研究采用三相交流电源的绝热时序电路.首先介绍了采用三相交流电源的双传输门绝热电路并分析其工作原理，在此基础上提出了性能良好的低功耗绝热D、T与JK触发器.使用绝热触发器设计时序系统的实例被演示.SPICE程序模拟表明，设计的电路具有正确的逻辑功能及低功耗的优点。     

GaAs MESFET differential pass-transistor logic

Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms     

Dynamic threshold pass-transistor logic for improved delay at lowerpower supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed     

A general method in synthesis of pass-transistor circuits

A general method in synthesis and signal arrangement in different pass-transistor network topologies is analyzed. Several pass-transistor logic families have been introduced recently, but no systematic synthesis method is available that takes into account the impact of signal arrangement on circuit performance. In this paper we develop a Karnaugh map based method that can be used to efficiently synthesize pass-transistor logic circuits, which have balanced loads on true and complementary input signals. The method is applied to the generation of basic two-input and three-input logic gates in CPL, DPL and DVL. The method is general and can be extended to synthesize any pass-transistor network.