采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

一种应用于开关电容电路的0.9 V自适应偏置OTA

设计了一种应用于开关电容电路的自适应偏置的低电压、低功耗开关运算跨导放大器。采用负阻负载技术和自适应偏置技术,分别提高了放大器的增益和转换速率;采用电流镜型OTA技术降低功耗,并通过控制开关关断非工作状态下的运放电源,进一步降低了功耗。新型开关电容共模反馈电路的共模电压可在一个时钟周期内快速稳定,不增加额外功耗,不限制输出摆幅。在SMIC 0.18 μm工艺下的仿真结果表明,OTA在0.9 V供电下,直流增益达60 dB,增益带宽积为1.81 MHz,转换速率为0.94 V/μs,功耗为4.16 μW。     

基于Switched-opamp的低功耗读出电路设计

利用开关运放技术对运放进行电源管理,实现了焦平面读出电路列运放的"休眠"-"唤醒"工作模式,使列运放仅在该列信号选通时工作.这种结构级功耗优化方法缩短了运放工作时间,降低了读出电路的功耗,适合低功耗系统应用要求.并设计了两种读出控制方案,对4×4元读出电路进行了瞬态分析.比照原有设计,该方法最多可以节省读出阶段列运放83%的功耗.     

标准数字工艺下16位精度低压低功耗ΣΔ模数调制器设计

针对输入信号频率在20 Hz～24 kHz范围的音频应用,该文采用标准数字工艺设计了一个1.2 V电源电压16位精度的低压低功耗ΣΔ模数调制器。在6 MHz采样频率下,该调制器信噪比为102.2 dB,整个电路功耗为2.46 mW。该调制器采用一种伪两级交互控制的双输入运算放大器构成各级积分器,在低电源电压情况下实现高摆率高增益要求的同时不会产生更多功耗。另外,采用高线性度、全互补MOS耗尽电容作为采样、积分电容使得整个电路可以采用标准数字工艺实现,从而提高电路的工艺兼容性、降低电路成本。与近期报道的低压低功耗ΣΔ模数调制器相比,该设计具有更高的品质因子FOM。     

一种低功耗可编程开关电容的分压电路

介绍了一种低功耗可编程分压电路,其静态功耗为零,输出电压不受工艺、温度影响,因此,在工程上具有广泛的应用前景。     

一种用于带通Σ-Δ调制器的25MHz低功耗开关电容谐振器

介绍了一种运用于带通Σ-Δ调制器的谐振频率为25MHz的低功耗开关电容DD谐振器电路.电路采用了运算放大器共享技术和双采样技术,同时对单元电路进行优化,达到功耗最小化.该谐振器电路采用SMIC 0.25μm混合信号CMOS工艺进行设计,整个电路模块面积仅为0.09mm2.测试结果表明,使用该谐振器电路的带通Σ-Δ调制器工作于100MHz采样频率时,对于信号带宽为1kHz的输入信号,调制器的输出在谐振频率处SFDR约为77dB.整个谐振器功耗为10.5mW.     

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

适合低功耗工作的MOS电荷泵

提出了两种适合在低功耗条件下工作的电荷泵电路,预充电电荷泵采用预充电机制提高了电荷泵的工作效率;而Domino电荷泵则采用内部电路控制电荷泵充电电容的充放电,不仅降低了功耗,同时均化了瞬态功耗.这解决了电荷泵在充电期间功耗过大的问题,使它们不仅能适用于有较强电源的电路,也可以在无源或低功耗的环境下工作.     

低噪声、低功耗微电容读出ASIC设计

针对差分电容式微电子机械系统(MEMS)加速度计,设计了一种低噪声、低功耗微电容读出专用集成电路(ASIC)。电路采用开关电容结构,使用相关双采样(CDS)技术降低电容-电压(C-V)转化电路的低频噪声和偏移电压。通过优化MEMS表头噪声匹配、互补金属氧化物半导体(CMOS)开关和低噪声运算放大器来降低频带内的混叠热噪声。采用电源开关模块和门控时钟技术来降低电路功耗,同时集成自检测电路和温度传感器。采用混合CMOS工艺进行流片加工,测试结果表明,优化后ASIC的电容分辨率为槡1.203 aF/Hz,系统分辨率为0.168 mg(量程2 g),芯片功耗约为2 mW。同时,该ASIC还具有很好的上电特性和稳定性。     

应用于可穿戴式设备的超低功耗SAR ADC研究与设计

针对便携式可穿戴移动设备的低功耗要求,提出了一种超低功耗逐次逼近型（SAR）模数转换器（ADC）。所提出的SAR ADC在数模转换器（DAC）电容阵列中设计了改进型电容拆分电路来降低系统的功耗和面积;并采用双尾电流型动态比较器架构降低比较器功耗。采用0.18μm CMOS工艺对所提出的SAR ADC进行设计并流片。测试结果表明在1.8V供电电压,采样率为50kHz的条件下,其有效位数为9.083位,功耗仅为1.5μW,优值55.3fJ,所设计的ADC适合于可穿戴式设备的低功耗应用。     

A novel CMOS exponential transconductor operating in weak inversion

A novel CMOS exponential transconductor which employs only three NMOS transistors operating in weak inversion, is presented. The main advantage of the proposed circuit is its wide range of exponential behaviour, which reaches up to five decades of current range, and above 10 μA to an input voltage range of 800 mV. The physical realisation is achieved in two forms: in the first one, the circuit is implemented with discrete MOS transistor arrays by CD4007 series; in the second one, the circuit is fully integrated in a 0.5 μm CMOS standard process. Simulated and experimental results of the proposed exponential transconductor are also presented.     

GaAs数字电路输入输出接口电路的设计

本文讨论了ＧａＡｓ电路和ＳｉＥＣＬ电路的输入输出接口问题，对ＧａＡｓ电路中ＢＦＬ、ＤＣＦＬ、ＳＤＦＬ等电路形式的典型输入输出接口电路进行了分析研究，用电路模拟程序计算并给出了ＢＦＬ输入输出接口电路的转移特性曲线。     

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

High-efficiency bipolar transconductors composed of hyperbolic function circuits with an intermediate voltage terminal and a triple-tail cell

Relatively high transconductance in bipolar devices contributes to the economy of power dissipation on analog integrated circuits. Recently, a high-speed transistor, such as the HBT attracts attention of researchers and developers in electronic communication industries and is expected to be applied to RF circuits. In this paper, high-efficiency bipolar transconductors are presented. The proposed circuits are composed of a hyperbolic function circuit with an intermediate voltage terminal and a triple-tail cell. The parameter values for linearisation are all integers. The values can be realised precisely. The linearity of the proposed transconductors is superior to the triple-tail cell. The linear input range is 1.5 times as wide as that of the conventional triple-tail cell. Nevertheless, the power dissipation is lower than the triple-tail cell. Further, sensitivity analysis shows that the proposed transconductors have lower sensitivity than the triple-tail cell. These properties are confirmed by SPICE simulation.     

Current-mode capacitorless integrators and differentiators for implementing emulators of fractional-order elements

Fractional-order capacitor and inductor emulator, implemented using current-mirrors as active elements and MOS transistors as capacitors, is introduced in this paper. Current-mirror integrators are used for performing the required current-mode integration/differentiation operation within the emulator stage. Also, a voltage-to-current converter, implemented using an Operational Transconductance Amplifier, is utilized for realizing the required interface of the input signal. Thus, the proposed emulator is simultaneously capacitorless and resistorless and offers the advantage of electronic tuning of the characteristics as well as of the type of the emulated fractional-order element. In addition, a modified version of the emulator that allows current excitation is proposed. The evaluation of the behavior of the proposed schemes has been performed using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35 μm CMOS process.     

Switched-Current Wave Filters with Reduced Number of Current Inversions

Switched-current wave filters offer very simple structures, as their main building blocks are current mirrors. On the other hand, the achieved accuracy is mainly degraded due to the effect of MOS transistor parameters mismatch. In this Letter, new configurations of serial and parallel adaptors that are used in the simulation of inductances and capacitors of the LC ladder prototype are introduced. These have been implemented using an appropriate sharing of the delay that should be presented between the incident and reflected waves at a port of adaptor, and a 3-phase clocking scheme. The number of required current inversions and consequently the effect of mismatching are reduced in the proposed configurations.     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

含源T形电路和含源Ⅱ形电路的等效变换

本文讨论了含源T形电路和含源Ⅱ形电路的等效变换,扩展了T形电路和Ⅱ形电路等效变换的内容。根据含独立电源二端口网络的特性方程,推导了含源T形电路和含源Ⅱ形电路等效变换的条件。含源T形电路和含源Ⅱ形电路等效变换的结果不具有唯一性,但可通过附加一些条件使变换结果唯一,本文给出了这些附加条件。并通过实例说明了推导结果的正确性。本文的分析对电路教学具有一定的价值,可供教学参考。     

Trading off circuit lines and gate costs in the synthesis of reversible logic

Motivated by its application in several emerging technologies, the synthesis of reversible circuits has received significant attention in the last decade. The proposed methods can roughly be divided into two different categories: (A) approaches ensuring the minimal number of circuit lines and (B) hierarchical approaches. Both synthesis paradigms have significant differences with respect to the gate costs and the number of lines in the resulting circuits. Hence, designers often have to deal with unsatisfactory results were either the gate costs or the number of circuit lines is disproportionately large.