Modified CFOA,its transpose,and applications

It is shown that the recently‐proposed modified current feedback operational amplifier (MCFOA) is quite a versatile element in that given a realization for a system function using MCFOAs, we can obtain three alternate realizations using the same MCFOA but by appropriately connecting the y, x, w, and z terminals of the MCFOA to the remaining part of the original realization. Using the results concerning the transpose of a multi‐terminal element, it is further shown that the transpose of an MCFOA is another MCFOA. Thus, using the results of transposition, given a voltage‐mode circuit using MCFOAs, we can directly obtain four current‐mode circuits using the same MCFOAs or vice versa. Copyright © 2015 John Wiley & Sons, Ltd.     

The design and implementation of a multi‐wing chaotic attractor based on a five‐term three‐dimension system

The last two decades have seen great progress about the generation and circuit realization of multi‐wing chaotic attractor. In this paper, several multi‐scroll chaotic attractors are generated from a five‐term system by adding a piecewise linear function. Moreover, some basic properties in terms of symmetry and dissipation, equilibrium points, eigenvalues of the Jacobian matrices, Lyapunov exponent spectrum, bifurcation diagram, and Poincaré map are studied. In particular, an analog circuit is designed to implement the proposed multi‐scroll attractors, which are different from the traditional attractors. Furthermore, an integrated circuit diagram is designed to realize the fractional‐order multi‐scroll attractors. Finally, the performed experimental results confirm the theoretical analysis, and our work lends itself to many potential applications in engineering. Copyright © 2015 John Wiley & Sons, Ltd.     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

Towards analog implementations of PWL two‐dimensional non‐linear functions

This paper deals with the circuit implementation of non‐linear algebraic bivariate functions. The synthesis procedure is based on a piecewise‐linear approximation technique and on a corresponding circuit architecture, whose basic element is a circuit block with the input/output function y(x) = max(0; x). Some known CMOS circuit structures that can be used to obtain such a block are considered, and their main advantages and drawbacks are pointed out. The static and dynamic features of both the single circuit block and the overall architecture for two‐dimensional PWL functions are illustrated by way of examples. Copyright © 2005 John Wiley & Sons, Ltd.     

Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.     

Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

This paper presents a fully digital architecture and its application specific integrated circuit implementation for computing multi‐input multi‐output (MIMO) piecewise‐affine (PWA) functions. The work considers both PWA functions defined over regular hyperrectangular and simplicial partitions of the input domains and also lattice PWA representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with application specific integrated circuit (ASIC) integrated in a 90‐nm complementary metal‐oxide semiconductor standard technology are provided. The proposed architecture is compared with other digital architectures in the state of the art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high‐performance and minimum unitary cost are required. Copyright © 2015 John Wiley & Sons, Ltd.     

On constructing complex grid multi‐wing hyperchaotic system: Theoretical design and circuit implementation

This paper further investigates some novel methods for generating complex grid multi‐wing hyperchaotic attractors from four‐dimensional (4D) quadratic hyperchaotic systems, based on our previous works. First, a modified double‐wing hyperchaotic Lü system by using non‐uniform variable scaling transformation is obtained, and n‐wing hyperchaotic system equipped with a duality‐symmetric multi‐segment quadratic function is also constructed. Then, by switching control in the z direction, mirror symmetry conversion and rotation transformation, three classes of n × m‐wing hyperchaotic systems are respectively realized. Finally, two types of improved module‐based circuits are designed for generating various grid multi‐wing hyperchaotic attractors. One characteristic of the proposed approaches lies in their generality, which is also suitable for constructing 4D grid multi‐wing hyperchaotic Lorenz and Chen systems. Both numerical simulation and circuit implementation have demonstrated the feasibility and effectiveness of the proposed approaches. Copyright © 2010 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A unified set‐theoretic approach to the analysis of PWL resistive circuits and composite N‐ports

We consider the search for all DC solutions of resistive piecewise‐linear (PWL) circuits and the analysis of the characteristics of resistive PWL composite N‐ports. These problems are unified from a theoretical and operating point of view by introducing the so‐called N‐augmented circuit, obtained from the N‐port by closing its ports with N norators. Set‐theoretic approach is used to describe the properties of the N‐augmented circuits leading to the formulation of a general DC analysis algorithm, based on linear programming techniques. The examples at the end of the paper show some practical and efficient application of the general DC analysis algorithm. Copyright © 2010 John Wiley & Sons, Ltd.     

General rational approximation of Gaussian wavelet series and continuous-time gm-C filter implementation

A general method of rational approximation for Gaussian wavelet series and Gaussian wavelet filter circuit design with simple g_m-C integrators is presented in this work. Firstly, the multiorder derivatives of Gaussian function are analyzed and proved as wavelet base functions. Then a high-accuracy general approximation model of Gaussian wavelet series is constructed, and the transfer function of first-order derivative of Gaussian wavelet filter is obtained using quantum differential evolution (QDE) algorithm. Thirdly, as an example, a fifth-order continuous-time analog first-order derivative of Gaussian wavelet filter circuit is designed based on multiple loop feedback structure with a simple g_m-C integrator as the basic blocks. Finally, simulation results demonstrate that the proposed method is an excellent way for the wavelet transform implementation. The designed first-order derivative of Gaussian wavelet filter circuit operates from a 0.53-V supply voltage and a bias current 2.5 nA. The power dissipation of the wavelet filter circuit at the basic scale is 41.1 nW. Moreover, the high-accuracy QRS detection based on the designed wavelet filter has been validated in application analysis.     

Application of class D power amplifiers in low power potentiostat circuits

In this paper a low power CMOS potentiostat is presented for energy limited applications such as human implantable sensors. The main focus is on using different techniques to reduce the power consumption at different circuit blocks, especially in the output stage that delivers power to the electrochemical cell. The proposed technique includes the use of a class D amplifier to reduce conduction power dissipation compared with conventional linear methods. Power dissipation has been improved by several other considerations such as elimination of opamp blocks which consume static power, avoiding current sampling stages and using dynamic latched comparators for loop error calculations. Closed loop stability problem and a low power solution to overcome this issue are addressed in the paper. The role of effective parameters such as inductor value, output MOSFET dimensions and clock pulse timing has been investigated and optimization considerations are used to achieve the low power potentiostat. Evaluation results show that a 12.96‐μW potentiostat with 1.03‐μW power dissipation and 89% efficiency is achievable with a linearity of R ² = 0.998. Copyright © 2016 John Wiley & Sons, Ltd.     

A systematic method for the development of a three‐phase transformer non‐linear model

In this work, a novel three‐phase transformer non‐linear model is developed. The proposed model takes into account the magnetic core topology and the windings connections. The non‐linear characteristic curve of the core material is introduced by its magnetization curve or by its hysteresis loop using the mathematical hysteresis model proposed by Tellinen or the macroscopic hysteresis model proposed by Jiles–Atherton. The eddy currents effects are included through non‐linear resistors using Bertotti's work. The proposed model presents several advantages. An incremental linear circuit, having the same topology with the magnetic circuit of the core, is used in order to directly write the differential equations of the magnetic part of the transformer. The matrix L _d that describes the coupling between the windings of the transformer is systematically derived. The electrical equations of the transformer can be easily written for any possible connection of the primary and secondary windings using the unconnected windings equations and transformation matrices. The proposed methods for the calculation of the coupling between the windings, the representation of the eddy currents and the inclusion of the core material characteristic curve can be used to develop a transformer model appropriate for the EMTP/ATP‐type programs. Copyright © 2009 John Wiley & Sons, Ltd.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Energy‐efficient single‐clock‐cycle binary comparator

A new fast low‐power single‐clock‐cycle binary comparator is presented. High speed is assured by using parallel‐prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.     

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

Recently several topological representations have been explored as alternatives to the conventional absolute‐coordinate representation for integrated circuit layout automation. Those topological representations, however, lack one or more aspects in capturing the solution space subject to symmetry constraints, which are abundant in analog layouts. In this paper, we explore the use of transitive closure graphs (TCGs) to represent analog placements, i.e. placements with symmetry constraints. We define a set of conditions so that a TCG satisfying these conditions, referred to as a symmetric‐feasible TCG, will correspond to a valid symmetric placement and vice versa. We then present an O(n²) algorithm, where n is the number of cells to be placed, to build a symmetric placement from a symmetric‐feasible TCG, a problem known as packing. We further describe a set of random perturbation operations on existing symmetric‐feasible TCGs to generate new symmetric‐feasible TCGs with time complexity of O(n) . This allows our TCG‐based symmetry‐aware analog placer to search only the symmetric‐feasible TCG solution space, leading to a substantial reduction of the search space and solution time. Experimental results on several analog circuits have confirmed the superiority of the TCG representation to the conventional absolute‐coordinate representation as well as several other topological representations in analog layout design. Copyright © 2008 John Wiley & Sons, Ltd.