一种双模式Flash控制器设计

以硬件直接实现固定的Flash编程操作是片内及片外Flash控制的常用方法。文中提出的双模式Flash控制器以Flash硬核模型为基础,组合了硬件直接实现硬核的编程操作和软件控制硬核的编程信号两种模式,实现了能以较快速度和较简单驱动控制Flash的逻辑和能以较高灵活性控制Flash的逻辑。两种模式使得Flash控制器具有一定的灵活性和快速实现性,其设计模式能适应更多Hash模型。     

Finding a k-tree core and a k-tree center of a tree network inparallel

A k-tree core of a tree network is a subtree with exactly k leaves that minimizes the total distance from vertices to the subtree. A k-tree center of a tree network is a subtree with exactly k leaves that minimizes the distance from the farthest vertex to the subtree. In this paper, two efficient parallel algorithms are proposed for finding a k-tree core and a k-tree center of a tree network, respectively. Both the proposed algorithms perform on the EREW PRAM in O(log n log n) time using O(n) work (time-processor product). Besides being efficient on the EREW PRAM, in the sequential case, our algorithm for finding a k-tree core of a tree network improves the two algorithms previously proposed     

CAN总线控制器IP核设计

设计了一个CAN总线控制器IP核。该IP核支持CAN总线标准帧和扩展帧两种报文格式,具有仅听模式和自测试模式,总线时序参数可配置,外部接口简单灵活,易于集成到各种CAN系统中。     

基于差别矩阵的属性核快速更新算法

核求解是粗糙集理论的重要内容之一，尽管在核求解问题上已有大量的研究成果，但有关核更新算法的报道却不多,有人提出一种在对象增加情况下核的增量式更新算法，但未讨论对象动态删除的情况．对此，提出一种基于差别矩阵的属性核快速更新算法——FUAC．该算法在更新差别矩阵时仅需删除某一行及某一列，或插入某一行,因而可有效提高核的更新效率．理论分析表明，该算法是有效可行的．     

Experimental approaches to protein folding based on the concept of a slow hydrogen exchange core

In a review of protein hydrogen exchange, we concluded that the slow exchange core is the folding core. By this we mean that the elements of secondary structure carrying the slowest exchanging backbone amides will tend to be the elements of secondary structure to fold first, that partially folded proteins will tend to be most organized in the core, and that peptides made to mimic the slow exchange core will tend to show nativelike structure. These generalizations have led us to ask several experimental questions that will be examined here: (1) In partially folded and unfolded proteins, how do the dynamics and structure of core regions differ from noncore regions? (2) Can we make protein 'core modules' as peptides corresponding to the slow exchange core? Can core modules be covalently linked to make a native state in which one conformation is significantly more stable than all other accessible conformations? (3) In a mutant perturbed outside the core, what are the effects on hydrogen exchange and folding?     

Inverse scattering by a multilayered obstacle

In this paper, we consider the inverse scattering problem of a plane acoustic wave by a multilayered obstacle which is important in various areas of imaging and nondestructive testing. When the core is penetrable (with transmission boundary conditions), we obtain that the core is determined uniquely by the corresponding far field pattern.     

Exploiting concurrency in the implementation of a discrete event simulator

Technological improvements in the use of computers through the better management of multithreading, such as with multi-core computers (core duo, core 2 duo, core 2 quad), have resulted in a reassessment of systems for simulating discrete events which can exploit these new capabilities. We consider the design and implementation of a process-oriented discrete event simulation library which makes exhaustive use of concurrence to improve the efficiency with which the simulations are executed.     

一种简易的UART IP核的设计与实现

文章主要介绍一种简易通用的UART IP核的设计。UART作为一种短距离、低成本通信的串行传输接口,随着嵌入式系统的迅速发展,已成为SoC(System on Chip)芯片中的一个重要部件,在数字通信中得到了广泛的应用。本设计在对UART的串行通信协议进行详细分析的基础上,采用Verilog HDL语言对ALTERA的Cyclone系列FPGA进行设计,用一片FPGA实现了UART的发送、接收和波特率发生等功能,并验证了结果。这种灵活的设计方法使整体设计紧凑、小巧,提高了系统的兼容性,节约了硬件成本,具有较强的推广价值。     

Large-eddy simulation of a turbulent jet and wake vortex interaction

In this study, temporal large-eddy simulations of the interaction between a turbulent jet flow and a trailing vortex are described. Three cases are analyzed: in the first one, the jet and the vortex axes are sufficiently well separated to not interact immediately, while in the second case, the distance between the jet and the vortex is reduced by half. In the last case the jet blows in the vortex core. In the two first cases, as the jet spreads it is progressively deflected by the continuous input of crossflow momentum. Thus it acquires azimuthal and radial components of velocity, causing the emergence of three-dimensional structures of azimuthal vorticity around it. When the jet and the vortex are superimposed, the turbulent kinetic energy does not increase, the vortex core is very buffeted. Numerical simulation results of the convection-diffusion of a passive scalar show that its distribution (initially in the jet) cannot penetrate inside the vortex core due to its solid rotation. For the cases where the jet is initially outside the vortex and when it is injected in the vortex wake, its value remains very high and cannot get out of the vortex core. This phenomenon confirms the existence of a stabilizing “dispersion buffer”, adjacent to the core, which prevents amplification of the turbulence generated inside the core.     

太比特核心路由器及其关键技术的研究

随着Internet的应用迅猛发展,主干网络上的信息流量急剧增长,对太比特(Terabit,即10^32 bit)核心路由器有迫切的需求,研究和开发太比特核心路由器已成为热点．综述了近年来在太比特核心路由器方面研究的最新成果,介绍了太比特核心路由器的新功能,并对新一代超高速太比特核心路由器的分布式体系结构进行了分析和研究,重点讨论了可扩展的多维交换结构．文中详细叙述了太比特核心路由器的关键技术,其中包括高速背板、高密度接口、路由表查找、数据包分类、资源管理、高性能核心路由器操作系统和核心软件以及QoS保证．最后,对太比特核心路由器技术的发展趋势进行了展望．     

一种面向不平衡分类数据的核求解算法

对基于差别矩阵的核求解方法而言，差别矩阵的规模是直接影响核求解效率的关键因素。为此，针对不平衡分类数据情况，提出一种基于多差别矩阵的核求解算法．该算法先按决策属性值划分对象集，进而建立任意两个不同对象集对应的差别矩阵，形成多差别矩阵，从而求出核．各差别矩阵因不平衡分类数据可有效降低其规模，提高核的求解效率．理论分析和实验结果表明算法是有效可行的．     

The Factor-2 Sign Detection Algorithm using a core function for RNS numbers

The determination of the sign of RNS (Residue Number System) numbers is not a trivial task. In this work, we have proposed an algorithm called the “Factor-2 Sign Detection Algorithm” for this purpose. This algorithm uses the core value of a RNS number to determine its sign. On the basis of the core values, two areas are defined as ambiguous and unambiguous. The sign of a RNS number with its core in an unambiguous area can be determined immediately but if the core of a RNS number is in an ambiguous area, it may require two to several iterations of the algorithm to determine its sign.     

一种基于改进差别矩阵的核增量式更新算法

提出一种基于改进差别矩阵的核增量式更新算法,主要考虑对象动态增加情况下核的更新问题．该算法在更新差别矩阵时仅须插入某一行及某一列,或删除某一行并修改相应的列,因而可有效地提高核的更新效率．理论分析和实验结果表明,该算法是有效可行的．     

一个利用模型驱动体系结构技术的分布式系统实现

模型驱动体系结构(ModelDrivenArchitecture)的提出是OMG对于分布式互操作问题提供的一条新的解决途径。该文对MDA的产生背景、核心技术以及互操作模型框架作了深入剖析。以此为基础,在一个软件系统的开发中应用了MDA和核心技术收到了良好的效果。获得了应用MDA的实践经验。     

Dynamic stability of a tapered symmetric sandwich beam

The stability of a fixed-free tapered symmetric sandwich beam under a pulsating axial force is studied. The effects of depth taper, shear parameter, core thickness and core density on the static buckling loads and the regions of parametric resonance are investigated.     

Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine

Hardware implementation of genetic algorithms (GAs) is gaining importance because of their proven effectiveness as optimization engines for real-time applications (e.g., evolvable hardware). Earlier hardware implementations suffer from major drawbacks such as absence of GA parameter programmability, rigid predefined system architecture, and lack of support for multiple fitness functions. In this paper, we report the design of an IP core that implements a general-purpose GA engine that addresses these problems. Specifically, the proposed GA IP core can be customized in terms of the population size, number of generations, crossover and mutation rates, random number generator seed, and the fitness function. It has been successfully synthesized and verified on a Xilinx Virtex II Pro Field programmable gate arrays device (xc2vp30-7ff896) with only 13% logic slice utilization, 1% block memory utilization for GA memory, and a clock speed of 50 MHz. The GA core has been used as a search engine for real-time adaptive healing but can be tailored to any given application by interfacing with the appropriate application-specific fitness evaluation module as well as the required storage memory and by programming the values of the desired GA parameters. The core is soft in nature i.e., a gate-level netlist is provided which can be readily integrated with the user's system. The performance of the GA core was tested using standard optimization test functions. In the hardware experiments, the proposed core either found the globally optimum solution or found a solution that was within 3.7% of the value of the globally optimal solution. The experimental test setup including the GA core achieved a speedup of around 5.16$,times$ over an analogous software implementation.      

一个新的二进制可辨识矩阵及其核的计算

首先用反例指出文献[4]中的利用R．Felix等人提出的二进制可辨识矩阵来求决策表的相对核的方法是错误的，然后给出一个新的二进制可辨识矩阵的定义和求核方法，并从理论上证明了方法的正确性。     

Low power integrated fluxgate sensor with a spiral magnetic core

Facing the new integrated applications, coordination between three parameters of the micro fluxgate sensor, namely, sensitivity, power consumption and operation range, is the key to make the applications come true. This paper reports a new low power micro integrated fluxgate sensor with low cost solution. A spiral electroplating permalloy magnetic core is introduced to reduce excitation current. Due to the design of little coils resistance and thick magnetic core, the fluxgate sensor exhibits a power consumption of 7.35 mW, a sensitivity of 117 V/T and a linear range of −200 to 200 μT. Compared with the constant-width magnetic core and the multi rectangular ring magnetic cores, experiment results show that the spiral magnetic core benefits both smaller excitation current and higher sensitivity. The newly developed fluxgate sensor maintains high sensitivity and wide linear range with low power consumption.     

Embedded coding using a mixed speech and audio coding paradigm

A two stage hybrid embedded speech/audio coding structure and algorithm are proposed. The first stage of the structure consists of a core speech coder which provides a minimum output bit rate and acceptable performance on clean speech inputs. The second stage is a perceptual/transform based coder which provides a separate optional bitstream for the enhancement of the core stage output.The two stage structure can be used to enhance the quality of an existing codec without modification of the original coding algorithm. In this regard it can be considered a value added option that can be used with a standard (existing) system. The structure can also be used in systems in which many users/systems force the coding algorithm to work simultaneously under multiple constraints of bitrate, complexity, delay, and coding quality.Informal testing of the algorithm has been done using ITU-T standard G.723.1 at 5.3 kb/s as a core coder. The maximum combined bitrate from the core and enhancement stages for the tests is 16 kb/s. The tests show that the second stage significantly improves the quality of the core output in the cases of music and speech with background noise. Compared to the non-embedded fixed rate standard LD-CELP G.728 at 16 kb/s, the quality of the two stage structure is generally lower on these inputs; the embedded feature does affect quality. On clean speech the quality of the two stage structure at 16 kb/s is close to if not better than that of G.728 at 16 kb/s.     

实时微处理器体系结构综述

实时应用已经成为嵌入式应用中一类快速崛起的典型应用。作为实时系统的核心部件,实时微处理器体系结构是微处理器领域的一个重要研究方向。与通用处理器追求最大吞吐量不同,实时处理器要求具有紧凑且可计算的最坏执行时间。传统的实时处理器往往采用较为简单的处理器结构,避免复杂结构引入执行时间的不确定性。随着实时应用对处理器性能需求越来越高,实时处理器正逐渐向多线程与多核结构发展。在多线程与多核处理器中,共享资源竞争导致实时系统的确定性变差,对实时处理器体系结构带来了更大挑战。对实时微处理器体系结构进行综述,首先从指令集、微体系结构、存储、I/O、任务调度等多个方面对传统实时处理器进行分析;然后分别对采用多线程与多核结构的高性能实时处理器展开分析;最后对几种商用实时处理器结构进行比较,总结实时处理器发展现状与未来发展趋势。