Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μ m CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven OTA and its applications

A new 0.5‐V bulk‐driven operational transconductance amplifier (OTA), designed in 50 nm CMOS technology, is presented in the paper. The circuit is characterized by improved linearity and dynamic range obtained for MOS devices operating in moderate inversion region. Some basic applications of the OTA such as a voltage integrator and a second‐order low‐pass filter have also been described. The filter is compared to other low‐voltage filters presented in the literature. Copyright © 2013 John Wiley & Sons, Ltd.     

Low‐voltage rail‐to‐rail switched buffer topologies

This paper presents some CMOS rail‐to‐rail low‐voltage (1.2 V) switched buffer topologies, to be used as input stages in switched‐opamp circuits. The main buffer is based on the use of an op‐amp featuring rail‐to‐rail input and output swing with constant transconductance over the input common mode voltage. The designed buffer exhibits a total harmonic distortion of about ‐61 dB for 5 MHz clock frequency with 2 V_pp input amplitude. Its characteristics have been compared with those of other rail‐to‐rail switched buffers, based on the main CMOS OTA (simple, symmetrical, Miller), showing good distortion even at frequencies in the MHz range and satisfying the requirements for the series switches. Copyright © 2001 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

Low‐noise low‐power front‐end logarithmic amplifier for neural recording system

In this work, a low‐power, low‐noise logarithmic preamplifier for biopotential and neural recording application is presented. The amplifier is based on a linear limit logarithmic amplifier technique, and an active filter as a DC cancellation filter has been included to its input in order to eliminate DC offsets, which are produced at the electrode–tissue interface. This system has been simulated in a UMC standard 90‐nm 1P9M CMOS process. Five dual gain stages are used to produce the required linear limit logarithmic amplifier. The dynamic range of the amplifier is measured to be 48 dB which covers the signals with amplitude from 20 μV to 5 mV. The amplifier consumes 23.5 μW from a 1.2‐V power supply and has a maximum gain of 69.8 dB. The simulated input referred noise is 5.3 μV over 0.1 Hz to 20 kHz. Copyright © 2012 John Wiley & Sons, Ltd.     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

On the input common‐mode voltage range of CMOS bulk‐driven input stages

In this paper the response of a bulk‐driven MOS Metal‐Oxide‐Semiconductor input stage over the input common‐mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35‐µm CMOS Complementary Metal‐Oxide‐Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source‐bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk‐driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5‐V second‐order operational transconductance amplifier (OTA)‐C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G _m), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5?μw. G _m variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is ?46 dB for 2.15 v_P-P differential output voltage signal with applying a 0.48 v_P-P input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.     

Mitigation of third‐harmonic voltage for three‐phase four‐wire distribution system based on a series active filter for neutral conductor

This paper proposes a series active filter for mitigation of the third‐harmonic voltage in a three‐phase four‐wire power distribution system in a building. The active filter which consists of a single‐phase inverter can suppress the harmonic voltage of the system. The active filter is characterized by acting not only as a capacitor but also as a resistor for the third‐harmonic components. A Hilbert transformer is applied to the controller of the active filter in order to realize accurate third‐harmonic detection on a single‐phase active filter. Measurement results of harmonic distortion of source voltage in a building is also shown in this paper. It is clarified in a simulation and experiment that the active filter can suppress the third‐harmonic voltage without increasing neutral conductor current. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 150(1): 62–70, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10379     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.