The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

用于先进CMOS电路的150mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

Isolation on Si wafers by MeV proton bombardment for RF integratedcircuits

This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 10¹⁷ cm^-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×10¹⁴ cm^-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×10¹⁵ cm ^-2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Hemisphere-shaped silicon crystal wafers obtained by plastic deformation and preparation of their solar cells

Hemisphere-shaped crystal wafers can be prepared by the plastic deformation of Si crystal wafers. To obtain hemispherical Si wafers, graphite convex and concave dies were used. A Si wafer was set between dies and pressed at high temperatures. The Si wafer was pressed by an overweight of 200 N at various temperatures. The deformation regions in which well-shaped (100) and (111) wafers can be obtained by plastic deformation were determined using parameters of thickness and temperature. In order to demonstrate that the shaped wafers are of sufficiently high quality to be used in the preparation of devices, solar cells were fabricated using the hemispherical Si wafers pressed at 1,120°C and 1,200°C. The conversion efficiency of the hemispherical solar cells is 8.5–11.5%. It was clarified from the conversion efficiency of solar cells that the quality of the shaped crystal wafers can be improved by a proper annealing process. Thus, the hemispherical shaped wafers are of high quality to be used in the preparation of devices.     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).     

The Effect of Thermal Shocks on the Stresses in a Sapphire Wafer

Sapphire wafers can experience temperature variations during processing in a furnace, which in turn can cause large deformation and stresses in the wafers. This paper aims to reveal the mechanism of stress development and evolution in sapphire wafers during thermal shocks, as well as the dependence of the stresses on some process parameters. Finite-element stress analysis was conducted on a single sapphire wafer subjected to thermal shocks. The results show that the thermal gradient in the radial direction induces high stresses even in mechanically unrestrained wafers. The largest stress components occur at the wafer edge as the largest normal stresses are circumferential; whereas the maximum tensile stress is realized upon cooling, the highest value of the maximum shear stress and the minimum compressive stress eventuate in the heating-up phase. The normal stresses have a parabolic distribution in the radial direction. It was found that holding the furnace temperature leads to a more uniform temperature distribution across the wafer but brings about higher tensile stresses in the cooling phase     

用单片清洗设备进行晶圆背面清洗

晶圆背面的污染降低了半导体器件的成品率,而当器件进入100nm技术节点之后成品率的降低便显得尤为重要。因此,目前众多的器件制造厂家就要求在进行片子正面清洗的同时对其背面也能够实现清洗。由Akrion公司制造的Mach2HP系统就是这样一种单片清洗设备,它具有清洗晶圆正反两面的功能。在起初评价时,设备经过了大量的粒子去除效率的变化。这种大量的变化使我们不能了解这种设备真实的清洗能力。氮化硅(Si3N4)粒子污染的晶片被用以进行粒子去除效率测试。我们发现有Si3N4粒子的晶片引起了背面粒子去除效率的变化。这种含Si3N4粒子的晶片是通过在裸芯片上沉积Si3N4粒子而特意准备的。我们发现,一些较大的Si3N4粒子在晶片清洗时又分解成更小的粒子。如若在清洗之后分解的粒子仍保留在晶片上,它们便会降低晶片总的粒子去除效果。因此,在这些粒子沉积到晶片上之前,这些粒子群需要进一步分解成实际的粒子。经过了解晶片的预习处理,我们实现了这种清洗设备背面清洗效果的评价。     

Doping of trench capacitors by rapid thermal diffusion

A new rapid thermal diffusion process for shallow, heavily doped trench junctions in high density dynamic RAMs is described. Planar dopant sources are formed by spin-coating rigid substrates, such as silicon wafers or solid dopant sources, with liquid dopants. Diffusion takes place at high temperatures when the source, placed in proximity to the silicon wafer, releases dopant via evaporation followed by diffusion to the silicon surface. Well-controlled, heavily doped shallow junctions are readily obtained for B, P, and As. The doping process is shown to provide uniform doping of high-aspect-ratio trenches. Process control is achieved by controlling the wafer temperature and duration of the process. Junction depths near 0.1 μm have been demonstrated over the entire surface of trenches 0.7 μm in diameter and 6 μm in depth     

超薄硅双面抛光片抛光工艺技术

MEMS器件、保护电路、空间太阳电池等的制作需要使用硅双面抛光片,并且要求抛光片的厚度很薄,传统的硅抛光片加工工艺已经不能满足这一要求.介绍了一种用于超薄硅单晶双面抛光片加工的抛光工艺方法.通过对硅片抛光机理[1],抛光方式、抛光工艺的研究和对抛光工艺试验结果的分析,解决了超薄硅单晶双面抛光片在加工过程中碎片率高、抛光...     

硅片表面磨削技术的应用研究

随着IC制造技术的飞速发展,为了增加IC芯片产量和降低单元制造成本,硅片直径趋向大直径化,原有的传统研磨工艺已不适应大直径硅片的加工,人们开始研究用硅片自旋转表面磨削方法来代替传统的研磨方法。通过实验的方法,对切割后的硅片表面进行磨削,获得了较理想的表面效果,达到了减少抛光去除量和抛光时间的目的。     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

超薄硅片贴膜抛光技术研究

伴随着集成电路芯片的不断轻薄化,各种高质量的超薄抛光片衬底需求日益增加.介绍了一种简捷、方便的手动贴膜方法,并将其应用在200μm厚7.6 cm硅单晶免清洗单面抛光片加工过程中,通过与粘蜡抛光相比较,发现贴膜抛光实用性更强、成品率更高且成本更低.     

Photoelastic stress evaluation and defect monitoring in 300-mm-wafer manufacturing

Process monitoring and tool characterization on product wafers require rapid non-contact and non-destructive evaluation methods. Because all process steps are more or less related to stress in the crystal, the photoelastic stress evaluation by infrared polarimetry is a suitable method for process screening both in wafer and IC manufacturing. It is shown that the full wafer imaging by scanning infrared depolarization can be applied to different steps of wafer manufacturing. After a short introduction into the method and technical realization of on-line photoelastic measurements, the concept of defect-related stress monitoring and process screening is demonstrated for slicing, grinding, lapping, etching, polishing and thermal treatment.     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated