Resistivity measurement of thin doped semiconductor layers by means of four point-contacts arbitrarily spaced on a circumference of arbitrary radius

The resistivity of a thin doped semiconductor layer or wafer measured in the vicinity of four point contacts placed on the semiconductor surface is shown to be independent of the relative distance between the contacts, provided the contacts are located on a circumference, and the distance to the boundary of the surface will not fall short of the greatest actual spacing between contacts. This method combines the advantage of the four probe resistivity measurement originally proposed by Valdés, that is the determination of ρ in a restricted layer region, with the advantage of arbitrary spacing of the probes, which characterizes van der Pauw's method. Experiments are in agreement with results obtained by the measuring methods of Valdés and van der Pauw.     

Resistivity and hall-effect topography on photoexcited semi-insulating GaAs

A new non-destructive method is presented for obtaining true resistivity (ρ), mobility(μ), and electron concentration(n) topography on photoexcited, semi-insulating GaAs. The method is based on the use of two perpendicular light slits, which join four removable In contacts on the periphery of the wafer to form a classical Greek-cross configuration. By placing contacts all around the periphery the whole wafer can be mapped. We give results for 1.1 μm photoexcitation on a 3′ low-pressure, liquid-encapsulated Czochralski wafer and compare with EL2 results on the same wafer. A by-product of the analysis is the determination of electron lifetime. Finally, the possibility of nondestructive dark electrical topography is discussed.     

Nondestructive defect characterization of SiC substrates and epilayers

This study presents a nondestructive and in-depth defect characterization method, based on the principle of polarized light microscopy (PLM), which can be used to quickly evaluate SiC substrates and epilayers. The developed PLM system has the capability to map, on a wafer scale, micropipes, elementary screw dislocations, and domain boundaries in SiC wafers. One unique feature of the PLM system is the ability to characterize the wafer with and without an epilayer, providing a newly found opportunity to investigate threading defect propagation in the overgrown epilayer. The correlation between SiC substrate defects and epilayer defects will be established.     

四探针和EIT测试微区薄层电阻的研究与进展

论述了一种测试大型硅片电阻率均匀性的新方法——电阻抗成像技术（EIT）。给出了四探针的基本原理,指出EIT的基本思想来源于四探针技术。对EIT的基本原理和重建算法在理论上进行了描述．提出可将其应用于微区薄层电阻测试,并对EIT在大型硅片微区薄层电阻率均匀性测试技术上的系统应用做了进一步探索。     

On contact resistance measurement using four-terminal Kelvinstructures in advanced double-polysilicon bipolar transistor processes

The contact between a polycrystalline silicon (polysilicon) layer and a silicon substrate is investigated for an advanced double-polysilicon bipolar transistor process. Contact resistances are measured using four-terminal cross bridge Kelvin structures. The specific contact resistivity of the interface and the sheet resistance of the doped substrate region directly underneath the contact are extracted using a two-dimensional simulation model originally developed for metal-semiconductor contacts. The extracted sheet resistance values are found to be larger than those measured using van der Pauw structures combined with anodic oxidation and oxide removal. During the fabrication of the contacts, epitaxial realignment of the polysilicon in accordance to the substrate orientation and severe interdiffusion of dopants across the interface take place, which complicate the characterization. The validity of the two-dimensional simulation model applied to the poly-mono silicon contact is discussed     

A comparative study of micropipe decoration and counting in conductive and semi-insulating silicon carbide wafers

Micropipes are considered to be one of the most serious defects in silicon carbide (SiC) wafers affecting device yield. Developing a method to count and map micropipes accurately has been a challenging task. In this study, the different etching behavior of conductive and semi-insulating wafers in molten potassium oxide (KOH) is compared. Micropipes and closed-core screw dislocations exhibit different morphology after etching and can be easily distinguished with a polishing process. Based on a new sample preparation procedure and a digital imaging technique, a novel method of efficiently and reliably mapping and counting micropipes in both conductive and semi-insulating SiC wafers is developed.     

高纯半绝缘SiC电阻率影响因素

采用物理气相传输(PVT)法进行高纯半绝缘SiC晶体生长,利用高温真空解吸附以及在系统中通入HCl和H2的方法,有效降低了系统中N、B和Al等杂质的背景浓度。使用二次离子质谱(SIMS)对晶体中杂质浓度测试,N、B和Al浓度分别小于1×1016、1×1015和2×1014 cm-3。对加工得到的晶片进行测试,全片的电阻率均在1×1010Ω·cm以上,微管密度小于0.02 cm-2,(004)衍射面的X射线摇摆曲线半高宽为34″。结果表明,该方法可以有效降低SiC晶体中N、B和Al等杂质浓度,提升SiC晶片的电阻率。使用该方法成功制备了4英寸(1英寸=2.54 cm)高纯半绝缘4H-SiC晶体。     

薄片样品霍尔迁移率的无接触测试和计算

设计了一种微波介质波导探头用于无接触测量半导体薄片样品的霍尔迁移率。它具有体积小、被测薄片样品大小不受限制等优点。在直流磁场变化时,无接触测试了一组n型硅薄片样品的横向磁阻,讨论了磁阻的计算方法及考虑样品的晶向后,由磁阻计算霍尔迁移率的方法,实验测试及计算结果是较为满意的。     

The annealing of phosphorus-ion-implanted cadmium telluride by a pulsed electron beam

A pulsed electron beam of 10 µs FWHM has been successfully applied to anneal phosphorus-implanted CdTe. The sheet resistance drops to 6.3 × 10²Ω/ from nearly infinite for the As-implanted wafers as the irradiation intensity exceeds 9.2 J/cm². A p-type carrier concentration as high as 3 × 10¹⁸cm^-3has been reached as measured by the van der Pauw and Hall techniques.     

无测试图形薄层电阻测试仪及探针定位

研制出检测U L SI芯片的薄层电阻测试仪,可用于测试无图形样片电阻率的均匀性,用斜置的方形四探针法,经显微镜、摄像头及通信口接入计算机,从计算机显示器观察,用程序及伺服电机控制平台和探针移动,使探针处于规定的位置,实现自动调整、测试;对测试系统中的探针游移造成的定位误差进行分析,推导出探针游移产生误差的计算公式,绘制了理论及实测误差分布图;测出无图形10 0 m m样品电阻率,并绘制成等值线Mapping图.     

Isolation on Si wafers by MeV proton bombardment for RF integratedcircuits

This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 10¹⁷ cm^-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×10¹⁴ cm^-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×10¹⁵ cm ^-2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value     

Characterization of deep centers in undoped semi-insulating GaAs substrates by normalized thermally stimulated current spectroscopy: Comparison of 100 and 150 mm wafers

A well-established characterization method for investigating deep traps in semi-insulating (SI) GaAs is thermally stimulated current (TSC) spectroscopy; however, TSC is not considered to be a quantitative technique because it involves carrier mobility, lifetime, and geometric factors, which are either unknown or poorly known. In this paper, we first show how to quantify a TSC spectrum, by normalizing with infrared (hv = 1.13 eV) photocurrent, and then apply this method (called NTSC) to study the lateral uniformity of the main deep centers across the diameters of undoped SI GaAs wafers. The wafers used in the study include both the standard 100 mm sizes and the new 150 mm variations, and are grown by both the low and high pressure liquid encapsulated Czochralski techniques. The results reveal that the 150 mm wafers have a worse NTSC uniformity for the main traps and a higher degree of compensation, as compared these parameters for the 100 mm wafers. In addition, nonuniformities related to the electric field effects on both the TSC spectrum and the low temperature photocurrent are found in the 150 mm wafer grown by the low pressure technique.     

GaP样品测试电极的制备

本文介绍了采用vandePauw法测量GaP材料电学性能参数时,电极材料的选取及实现电极与样品良好欧姆接触的电极制备条件。     

半绝缘SiC单晶电阻率均匀性研究

采用非接触电阻率面分布(COREMA)方法对本实验室生长得到的2英寸(50 mm)4H和6H晶型半绝缘SiC单晶片进行电阻率测试,结果发现数据的离散性大,低者低于测试系统下限105Ω.cm,高者高于其上限1012Ω.cm,甚至在同一晶片内会出现小于105Ω.cm,105~1012Ω.cm和大于1012Ω.cm的不同区域,而有的晶片则电阻率的均匀性较好。将SiC电阻率测试结果与二次离子质谱(SIMS)对晶体内主要杂质V,B和N含量测试结果相结合,初步探讨得到引起掺钒SiC单晶电阻率的高低及均匀性的变化由补偿方式决定,在深受主补偿浅施主模式下,V的浓度控制在2×1016~3×1017cm-3,N的浓度控制在1×1016cm-3左右,深受主钒充分补偿浅施主氮,制备得到的SiC单晶具有半绝缘性,且电阻率均匀性好。     

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed     

Fabrication of undoped semi-insulating InP by multiple-step wafer annealing

Recently, it was found that undoped semi-insulating InP can be reproducibly obtained by wafer annealing at 950°C for 40 h under phosphorus vapor pressure of 1 atm. Resistivity variation across the 50 mm diameter wafer after this annealing process, however, was in the range of 22.5–53.7%. In order to realize the fabrication of undoped semi-insulating (SI) InP with uniform electrical properties, multiple-step wafer annealing (MWA) procedure has been applied for the first time. It was found that two-step wafer annealing at 950°C for 40 h under phosphorus vapor pressure of 1 atm and at 807°C for 40 h under phosphorus vapor pressure ranging from 30 to 50 atm, was effective in improvement of the uniformity of the electrical properties of undoped SI InP. By the present MWA, the resistivity variation of 8–12% and the mobility variation of 2–4% could be obtained for 50 mm diameter wafers.     

电阻率对电容法测Si片厚度的影响

在对电容法测量Si片厚度的原理分析基础上,根据电阻率与介质介电常数ε的对应关系,分析了用电容法测试Si片厚度时,电阻率及电阻率均匀性对测试结果的影响,并采用千分尺(有接触测试)、ADE6034及Wafer Check 7000(电容法测试)分别对不同电阻率及电阻率均匀性的样品进行测试比对。实验结果证明,电容法可以测量高电阻率Si片的厚度等几何参数,但不能测量电阻率均匀率较差的Si片。同时,校正电容法测量设备时,以校正样片电阻率与被测Si片电阻率范围接近为原则。     

InSe Schottky Diodes Based on Van Der Waals Contacts

2D semiconductors are excellent candidates for next‐generation electronics and optoelectronics thanks to their electrical properties and strong light‐matter interaction. To fabricate devices with optimal electrical properties, it is crucial to have both high‐quality semiconducting crystals and ideal contacts at metal‐semiconductor interfaces. Thanks to the mechanical exfoliation of van der Waals crystals, atomically thin high‐quality single‐crystals can easily be obtained in a laboratory. However, conventional metal deposition techniques can introduce chemical disorder and metal‐induced mid‐gap states that induce Fermi level pinning and can degrade the metal‐semiconductor interfaces, resulting in poorly performing devices. In this article, the electrical contact characteristics of Au–InSe and graphite–InSe van der Waals contacts, obtained by stacking mechanically exfoliated InSe flakes onto pre‐patterned Au or graphite electrodes without the need for lithography or metal deposition is explored. The high quality of the metal‐semiconductor interfaces obtained by van der Waals contact allows to fabricate high‐quality Schottky diodes based on the Au–InSe Schottky barrier. The experimental observation indicates that the contact barrier at the graphite–InSe interface is negligible due to the similar electron affinity of InSe and graphite, while the Au–InSe interfaces are dominated by a large Schottky barrier.     

半绝缘半导体切片电阻率无接触测定方法研究

与很多测试方法一样,电阻率是通过流过电接触样品的电流,测出其电压下降值来测定的.文中通过对无接触和接触两种主要测试方法的研究对比,探讨了用电容式探测器对半绝缘半导体切片电阻率的无接触测定,并论述了其测试原理、测试所用电容器、测试条件、测试过程及结果计算.     

Four-point probe characterization of 4H silicon carbide

We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 10¹⁸ cm⁻³ are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 10¹⁴ cm⁻³ gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 10¹² Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.