A Si bipolar 21-GHz/320-mW static frequency divider

A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V_ce=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz)     

75 GHz ECL static frequency divider using InAlAs/InGaAs HBTs

A 75 GHz static frequency divider in InAlAs/InGaAs transferred-substrate heterojunction bipolar transistor (HBT) technology is reported. This is the highest reported frequency of operation for a static frequency divider. The circuit has 60 transistors and dissipates 800 mW. The divider was operated at a clock frequency of 5.0 to 75 GHz     

80 GHz 4:1 frequency divider IC using nonself-aligned InP/InGaAsheterostructure bipolar transistors

80 GHz operation has been attained for a divide-by-four frequency divider IC fabricated with non-self-aligned InP/InGaAs heterostructure bipolar transistors. To the authors' knowledge, this is the fastest digital frequency divider IC reported to date. The measured maximum toggle frequency of 80 GHz was the upper limit of the measurement setup     

Static 7 GHz frequency divider IC based on a 2 ?m Si bipolar technology

A static 8:1 frequency divider IC operating at up to 7 GHz has been realised using a preproduction silicon bipolar technology with 2 ?m lithography. This technology is characterised by a self-aligned double polysilicon emitter-base structure and oxide wall isolation. The high upper frequency limit, not yet achieved with comparable 2 ?m technologies, was attained by careful circuit design and optimisation.     

一种宽带的InGaP/GaAs HBT 再生频率分频器

A dynamic divide-by-two regenerative GaP/GaAs heterojunction bipolar transistors （HBTs） frequency divider （RFD） is presented in a 60-GHz-fT Intechnology. To achieve high operation bandwidth, active loads instead of resistor loads are incorporated into the RFD. On-wafer measurement shows that the divider is operating from 10 GHz up to at least 40 GHz, limited by the available input frequency. The maximum operation frequency of the divider is found to be much higher than fT/2 of the transistor, and also the divider has excellent input sensitivity. The divider consumes 300.85 mW from 5 V supply and occupies an area of 0.47 × 0.22 mm^2.     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

A Wide Locking-Range Frequency Divider for LMDS Applications

A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications.     

96-GHz static frequency divider in SiGe bipolar technology

A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).     

超高速双层多晶硅发射极晶体管及电路

报道了双层多晶硅发射极超高速晶体管及电路的工艺研究．这种结构是在单层多晶硅发射极晶体管工艺基础上进行了多项改进,主要集中在第一层多晶硅的垂直刻蚀和基区、发射区之间的氧化硅、氮化硅复合介质的L型侧墙形成技术方面,它有效地减小了器件的基区面积．测试结果表明,晶体管有良好的交直流特性．在发射区面积为3μm×8μm时,晶体管的截止频率为6.1GHz．19级环振平均门延迟小于40ps,硅微波静态二分频器的工作频率为3.2GHz．     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

A 50 GHz Divide-by-4 Injection Lock Frequency Divider Using Matching Method

A fully integrated divide-by-4 frequency divider has been designed, fabricated, and measured in the standard bulk 0.18-m complementary metal-oxide semiconductor (CMOS) technology. A newly proposed matching technique was used to eliminate the unwanted low frequency mixing terms at the common node of the circuit so as to achieve a high division ratio of 4. The frequency divider exhibits a measured operation range of 5 GHz from 45.9 to 50.9 GHz. It consumes a dc power of 7.56 mW at a 1.2 V supply in the steady state operation. The phase noise of the free running divider is 88.51 dBc/Hz at 1 MHz offset and the locked divider is 110.74 dBc/Hz at 1 MHz offset. The chip size is only 0.35 mm 0.5 mm including the pad frame. To our knowledge, this divider has the highest operation frequency to date among the high division ratio injection-lock type frequency dividers in commercial CMOS 0.18-m process.     

3GHz硅双极型微波静态分频器的设计

本文报道了一种超高速ＥＣＬ静态二分频器；介绍了该分频器的核心器件─—ＮＰＮ晶体管的结构和实现该结构的有关先进工艺，包括深槽隔离、多晶硅发射极、钻硅化物和浅结薄基区等；使用这种多晶硅发射极晶体管，３ｐｍ特征尺寸设计的１９级环形振荡器的平均门延迟小于５０ｐｓ．讨论了提高分频器工作频率的一些有效方法并给出了３．２ＧＨｚ硅静态分频器的电路设计和版图设计．     

High-frequency performance of submicrometer channel-length siliconMOSFETs

Polycide-gate silicon n-channel MOSFETs were fabricated on the basis of a standard 0.5-μm MOS technology and measured over the 1.5-26.5-GHz frequency range, in order to investigate the effects of channel-length reduction on device behavior at high frequency. Excellent microwave performances were obtained with a maximum operating frequency (f_max) and a unity-current-gain frequency f _t near 20 GHz for 0.5-μm-gate-length NMOS devices. An equivalent circuit for a MOSFET with its parasitic elements was extracted from measured S-parameter data. The influence of gate resistance, gate-to-drain overlap capacitance, substrate conductivity, and the transit-time effect between the source and drain on microwave characteristics was analyzed     

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.     

High-performance implanted base silicon bipolar technology for RFapplications

A 0.4 μm silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above     

Gigabit logic bipolar technology: advanced super self-aligned process technology

A practical bipolar logic circuit, a three-stage frequency divider, has been made with advanced super self-aligned process technology (a halfmicron bipolar technology), which has been operated at clock frequencies up to 5.5 GHz.     

10.7 GHz frequency divider using double layer silicon bipolarprocess technology

A high-speed bipolar process is described which offers high performance, low capacitances and high packing densities. The performance of the process is demonstrated by a 1/8 frequency divider operating at a room temperature frequency of 10.7 GHz. This is considered to be the fastest for any silicon bipolar circuit     

A 5-mA 1-GHz GaAs dual-modulus prescalar IC

A 1-GHz GaAs dual-modulus divide-by-128/129 prescalar IC with current drain of only 5 mA has been developed. Its current drain is one-sixth that of commercially available Si bipolar ICs used in 800-MHz band mobile radio systems. Five-level series gate low-power source-coupled FET logic (LSCFL) and the 0.50-/spl mu/m gate buried P-layer SAINT (BP-SAINT) process technology have been used to achieve this small current drain together with high-speed operation. A high-speed divide-by-4/5 modulus divider (3.1 GHz, 13 mA) and divide-by-32 divider (6.1 GHz, 19 mA) has also been designed and fabricated. These prescalars are suitable for use as synthesizers in mobile communication systems.     

Multifunction silicon MMIC's for frequency conversion applications

The application of advanced silicon bipolar IC technology to multifunction microwave monolithic integrated circuits (MMICs) is demonstrated. The modeling, design, and testing of two silicon MMICs for frequency conversion applications are illustrated. The first product is a wideband frequency doubler with conversion gain, 20-dBc rejection of harmonics, and a 2-GHz bandwidth. The second product is a wideband vector demodulator (or image reject mixer) that utilizes an onchip digital frequency divider to generate 0° and 90° local oscillator (LO) phases from 0.05 to 1.5 GHz. Both products operate from a single 5-V supply, are load insensitive, require no external baluns, and are packaged in 180-mil hermetic packages. These frequency conversion MMICs and others currently under development have been prototyped on the analog silicon transistor array starCHIP-1, which is also described     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.