一种新的终止LDPC迭代译码算法

在传统的卫星广播系统中,信道纠错通常采用BCH码级联LDPC码的方案以达到良好的误码率性能,例如DVB-S2系统。作为内码的LDPC码通常采用迭代译码,且迭代次数较高才能实现比较好的系统性能。借助BCH级联LDPC的结构,文中提出了将BCH检错嵌套进LDPC每一次迭代译码过程中的新的迭代译码结构。仿真结果表明,新算法以较低的BCH码检错运算复杂度换取了LDPC码迭代次数的明显下降,从而极大降低了迭代译码总体复杂度和译码时延,且整体纠错性能与原始LDPC译码后BCH纠错的算法相比基本保持不变。     

65nm工艺下面积功耗优化的BCH电路设计

在65 nm工艺下实现了最大纠正84 bit错误的带循环冗余码(CRC)校验保护功能的BCH(32767,16416)纠错电路,纠错能力可配置。该设计采用频率比为1∶4的两种工作时钟,最高工作频率为100 MHz和400 MHz。两种工作频率的合理组合降低译码运算的延迟,提高固态硬盘读写数据的性能,同时提供了分时复用的可能。通过复用伴随式计算、关键方程系数求解(iBM算法)和钱搜索过程中的有限域乘法运算单元优化芯片面积。通过调整钱搜索的起始位置,实现编码和伴随式计算的求余电路复用,实现面积和功耗的优化,最终芯片面积节省了27%,功耗降低了26%。     

一种RS码译码器的硬件实现方法

提出了一种RS系统码译码器的硬件实现结构。译码器采用时域译码算法,主要包括有限域并行乘法器、BM迭代算法、适合于缩短码的钱氏搜索算法、错误值计算的硬件电路,其运算结构规则,具有一定的通用性,因此适合于VLSI实现。     

BCH-Turbo码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案.本方案采用BCH码作为Turbo迭代译码的停止准则,并对每一个分量译码器结果都进行判断,可提前停止迭代.通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低,Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降.本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响.     

BCH-Turbo编码的设计与仿真实现

本文针对Turbo码在低信噪比下迭代次数多、译码时延长问题,在分析了Turbo码的编译码原理和算法基础上,提出一种可以有效降低平均迭代次数、减少译码时延的基于BCH迭代停止准则的Turbo码迭代译码的设计方案。本方案采用BCH码作为Turbo迭代译码的停止准则。并对每一个分量译码器结果都进行判断。可提前停止迭代。通过Monte Carlo仿真表明在AWGN信道下,误码率有所降低。Turbo码译码的平均迭代次数与交叉熵准则相比有明显下降。本文还分析了BCH码编码效率和分组长度的选择对系统性能的影响。     

π-旋转LDPC码的高效并行编译码结构设计

该文设计了一种π-旋转LDPC码并行编/译码电路结构.利用π-旋转LDPC码的规则化旋转结构,编码、译码电路实现了分组并行处理.在信息迭代过程中,利用校验矩阵的旋转结构,使用一种二维数组存储译码迭代信息,不需要地址索引、只需通过映射即可取出所需参与运算的变量/校验信息,实现了迭代信息的分散存储、映射提取.这种分组、旋转...     

乘积码迭代译码算法研究

介绍了在分组码的软输入软输出译码基础上以扩展BCH码为子码的乘积码的迭代译码算法,提出了在高带宽利用率调制方式下的算法应用方式,并给出了仿真结果。最后与传统的并联卷级码代译码方案比较,发现在高编码效率时,乘积码迭代译码方案有着较好的应用性。     

高速Berlekamp-Massey算法结构及电路实现

介绍了两种用于二进制BCH解码器的高速Berlekamp—Massey算法实现方案。在加入寄存器以减少关键路径的延时从而提高电路速度的基础上，一种方法是采用有限域乘法器复用的方法降低电路的复杂度；另一种方法则通过对有限域乘法器进行流水线设计，进一步提高电路的工作速度，实现超高速应用。设计中充分利用了二进制BCH码中Berlekamp—Massey算法迭代计算时修正值间隔为零的性质，用超前计算的方法减少了运算周期的增加。提出的方案可用于设计高速光通信系统的信号编解码芯片。     

符合分包遥控标准的快速BCH（63，56）译码方法

BCH码作为一种性能优良的分组码,具有严格的代数结构,纠错性能很强,构造方便,编码简单。同时BCH译码过程繁杂,计算复杂,为其应用带来不便。CCSDS分包遥控体制建议使用改进的BCH（63,56）码对含噪的物理信道进行差错控制。本文提出一个快速的BCH（63,56）译码方法,该方法具有译码结构简单,便于软件、硬件实现,译码速度快,运算简单等优点。本文详细描述了BCH（63,56）译码方法的算法细节并利用FPGA实现。     

一种BCH码编译码器的设计与实现

二元BCH码具有良好的代数结构和纠错能力,是应用最为广泛的码类之一。在此介绍了BCH（255,223）的编译码算法和硬件实现方法,针对二元BCH码提出了一种适合硬件模块化设计的BM迭代译码算法,并基于Xilinx公司的xc5vlx110t实现了BCH（255,223）纠错编译码。仿真结果表明,采用此方法实现的编译码器具有速度快、构造简单、性能稳定以及结构灵活的优点。目前该编译码器已成功用于某数字电台系统中。     

Generalized Low-Error Area-Efficient Fixed-Width Multipliers

In this paper, we extend our previous methodology for designing a family of low-error area-efficient fixed-width two's-complement multipliers that receive two$n$-bit numbers and produce an$n$-bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to low-error area-efficient fixed-width multipliers suitable for very large-scale integration implementation and digital signal processing application. Via the proposed Type 1 8$times$8 fixed-width multiplier, the reduction of the average error can be improved by 88% compared with the direct-truncated (D-Truncated) multiplier. It is also shown that the same proposed multiplier leads to 32.75% reduction in area compared with the standard multiplier.     

Efficient pipeline FFT processors for WLAN MIMO-OFDM systems

The most area-efficient pipeline FFT processors for WLAN MIMO-OFDM systems are presented. It is shown that although the R2/sup 3/SDF architecture is the most area-efficient approach for implementing pipeline FFT processors, RrMDC architectures are more efficient in MIMO-OFDM systems when more than three channels are used.     

基于改进混合式CORDIC算法的 直接数字频率合成器设计

 提出一种新的面积优化的直接数字频率合成器设计方案.采用改进混合式CORDIC算法,通过削减旋转相位判断电路和乘法单元,改进和调整相位旋转误差,并利用简单的移位和加/减电路完成复杂的幅度修正,降低了电路复杂度,缩减了电路规模.结构上采用流水线式多级循环迭代技术,实现移位和加/减电路的高度复用.实验结果表明本方法输出频谱杂散小于-70dB,并在运算速度和资源利用率上具有一定的优势.该设计已成功用于宽带网络SoC芯片的频率调制模块.     

Small area parallel Chien search architectures for long BCH codes

To implement parallel BCH (Bose-Chaudhuri-Hochquenghem) decoders in an area-efficient manner, this paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.     

An area-efficient very large scale integration architecture for modified Euclidean algorithm with dynamic storage technique

A Modified Euclidean (ME) algorithm has been used to solve the key equations in Reed-Solomon (RS) decoding. In this article, the degree properties of the ME algorithm are derived. On the basis of the degree properties, an area-efficient very large scale integration (VLSI) architecture with dynamic storage technique is proposed to perform the ME algorithm. The dynamic storage technique is used to avoid data exchange and save hardware resources. The proposed architecture with dynamic storage technique can reduce 50% computation hardware area and about 30% memory hardware area. VLSI implementation results of different RS codes show that the proposed architecture is significantly area-efficient, especially for RS codes with long code lengths.     

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS

This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-$muhbox m$process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095$hbox mm^2$die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply.     

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.     

A foresighted strategy for greed-based multicasting algorithms in all-optical mesh networks

For abundant bandwidth, all-optical mesh networks have been more and more important in communications, and multicasting is one of the key technologies to that. The problem to find a minimum multicasting tree is NP-hard, and all the existing algorithms are heuristics. Most of them are based on the idea of being greed. A greedy idea is always shortsighted. While it could get a good local effect, it would obtain a somewhat bad global performance. In this article, we propose a foresighted strategy for greed-based multicasting algorithms. With the co-action of the greedy idea and a foresighted strategy, a multicasting algorithm can get a good local and global performance simultaneously. We introduce the strategy by embedding it in the Member-Only algorithm and investigate two indexes, the average cost of all multicasting requests and the blocking rate of the whole network. Simulation results show that, with the presence of the proposed foresighted strategy, these two targets are all obviously decreased.     

Synthesis of area-efficient and high-throughput rate data formatconverters

This paper proposes two design methodologies for synthesis of area-efficient data format converters (DFCs) with high throughput rate. DFCs are grouped into various classes according to the specification of design parameters. The first design methodology is suitable for design of many representative classes of DFCs. The designs using this methodology are based on a two-dimensional (2-D) architecture. They have maximum throughput rate and are area-efficient. Various design examples are shown to demonstrate improved performance, flexibility and usefulness of this design methodology. For several representative problems, the area requirements of our designs are compared against those obtained by earlier design methodologies. For all the problems considered, this methodology leads to compact designs. The second design methodology employs an architecture using dual buffers. The simple and regular architecture using dual buffers leads to area-efficient DFCs. The design procedure using this methodology is simple and can reduce the design effort in many applications     

Area-efficient architectures for the Viterbi algorithm II.Applications

In part I the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm were established. Area-efficient architectures for practical codes are presented here to illustrate the design procedures and demonstrate the favourable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes are presented. The application of the area-efficient techniques to codes with a very large number of states, codes with time-varying trellises, and a programmable Viterbi decoder is discussed