A method for the prediction of hot-carrier lifetime in floating SOINMOSFETs

A concept was presented for the prediction of the device lifetimes for the hot-carrier effect (hot-carrier lifetimes) in floating SOI MOSFETs. The concept is that hot-carrier lifetimes in floating SOI MOSFETs can be predicted by estimating the hole current. In order to verify the validity of this concept, the hole current was investigated using device simulation. The results showed that the ratio of the hole current to the drain current in a floating-body SOI MOSFET is approximately equal to the ratio of substrate current to drain current in a body-tied one. Based on this fact, a method for accurately predicting the hot-carrier lifetime in floating-body SOI MOSFETs was proposed. The hot-carrier lifetime predicted with this method agreed well with the experimental results. This study showed that only the drain current difference between floating and body-tied structures results in lifetime differences, and there is no special effect on hot-carrier degradation in floating SOI MOSFETs. In this prediction, therefore, floating SOI MOSFETs can be treated in the same way as bulk MOSFETs. Hot-carrier lifetimes in floating SOI MOSFETs can be predicted using the hole current, while substrate currents are used in bulk MOSFETs     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs

A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs.      

Low-voltage transient bipolar effect induced by dynamicfloating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems     

A comparative analysis of the dynamic behavior of BTG/SOI MOSFETsand circuits with distributed body resistance

To examine the dynamic nature of body-tied-to-gate (BTG) partially depleted SOI MOSFETs, CMOS inverter circuits (nine-stage ring oscillators and 50-stage chains) are simulated with SOISPICE, accounting for the BTG distributed body resistance. Due to the physical nature of the UFSOI model in SOISPICE, both the static and dynamic characteristics of the BTG device, contrasted to floating-body (FB) and body-tied-to-source (BTS) SOI MOSFETs, are faithfully revealed. Results give insight on previously measured, yet inadequately explained, dynamic behavior of the BTG device. Further, problematic hysteretic behavior associated with the dynamic operation of the device with realistic body sheet resistance is described, suggesting design constraints on the maximum device width. Finally, a performance assessment of the BTG device configuration in ultra-low-power CMOS digital applications is offered and compared with FB and BTS, indicating that the optimal configuration is in fact application-specific     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

Analysis and control of floating-body bipolar effects in fullydepleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible     

Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs

Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility enhancement, band offsets, junction capacitance, and self-heating effects. All of the floating-body current components in conventional SOI structure, which are generation/recombination current, reverse-bias (band-to-band and trap-assisted) junction tunneling currents, gate-induced drain leakage current, gatebody oxide tunneling current, and impact ionization current are applied to the SSOI device, and their effects are discussed. The model validity is confirmed by fabricated 70?nm bulk-Si (control) and strained-Si devices.     

Enhanced substrate current in SOI MOSFETs

This letter reports an enhanced substrate current at high gate bias in SOI MOSFETs. A comparison between coprocessed bulk and partially depleted SOI MOSFETs is used to present the enhancement unique to SOI devices and demonstrate the underlying mechanism. Other than electric field, a new source for carrier heating in the channel, i.e., self-lattice heating, is found to be responsible for the excess substrate current observed. The impact of this phenomenon on SOI device lifetime prediction and compact modeling under dynamic operating conditions typical of digital circuit operation is described. This SOI-specific enhancement must be considered in one-to-one comparisons between bulk and SOI MOSFETs regarding hot-carrier effects     

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage     

Physical noise modeling of SOI MOSFETs with analysis of theLorentzian component in the low-frequency noise spectrum

The implementation of a general physics-based compact model for noise in silicon-on-insulator (SOI) MOSFETs is described. Good agreement is shown between model-predicted and measured low-frequency (LF) noise spectra. In particular, the behavior of an excess Lorentzian component that dominates the LF noise spectra of SOI MOSFETs is investigated. Shot noise associated with the generation and removal (via recombination or a body contact) of body charge is shown to underlie the behavior of the Lorentzian in both floating-body and body-tied-to-source SOI MOSFET's operating under partially depleted or “mildly” fully depleted conditions; the Lorentzian is suppressed when the body is “strongly” fully depleted. Good physical insight distinguishes the behavior of the Lorentzian components in all these devices, and predicts the occurrence of additional excess noise sources in future scaled technologies. Simple analytic expressions that approximate the full model are derived to provide the insight     

Analytical threshold voltage model for ultrathin SOI MOSFETsincluding short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V_th- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V_th lowering for drain voltages larger than V_dk≃B_i.λ_i/3, where B_i is the impact ionization coefficient, and λ_i is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length λ     

Effect of floating-body charge on SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V_T and off-current I_0FF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V_T and I_0FF due to hysteretic floating-body charge are quantified for devices in L _eff=0.2- and 0.1-μm design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-μm design space     

Grasping SOI floating-body effects

It is important to understand what the floating-body effects are and how they affect device and circuit behavior. In this regard, this article qualitatively explains the device physics underlying DC and transient floating-body effects, clearly implying their influence on circuits, and thereby giving good insight into PD/SOI CMOS design issues. The article also notes special but practical device and circuit designs for controlling floating-body effects, showing through simulation how PD/SOI offers a significant performance advantage over bulk silicon in low-voltage applications, thereby conveying an assurance that reliable SOI CMOS design is feasible     

SOI器件中瞬态浮体效应的模拟与分析

针对 SOI器件中的瞬态浮体效应进行了一系列的数值模拟 ,通过改变器件参数 ,比较系统地考察了 SOI器件中瞬态浮体效应 ,同时也研究和分析了瞬态浮体效应对 CMOS/SOI电路 (以环振电路为例 )的影响 ,并提出了抑制器件浮体效应的器件结构和参数优化设计 .     

一种采用局域注氧技术制备的新型DSOI器件

为了克服传统SOI器件的浮体效应和自热效应,采用创新的工艺方法将低剂量局域SIMOX工艺及传统的CMOS工艺结合,实现了DSOI结构的器件.测试结果表明,该器件消除了传统SOI器件的浮体效应,同时自热效应得到很大的改善,提高了可靠性和稳定性.而原先SOI器件具备的优点得到了保留.     

一种采用局域注氧技术制备的新型DSOI器件

为了克服传统SOI器件的浮体效应和自热效应,采用创新的工艺方法将低剂量局域SIMOX工艺及传统的CMOS工艺结合,实现了DSOI结构的器件.测试结果表明,该器件消除了传统SOI器件的浮体效应,同时自热效应得到很大的改善,提高了可靠性和稳定性.而原先SOI器件具备的优点得到了保留