AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

Floating body induced pre-kink excess low-frequency noise insubmicron SOI CMOSFET technology

The well-known post-kink Lorentzian-like noise overshoot has been empirically correlated to the ac kink effect in the SOI CMOSFET in the past. This work demonstrates the existence of a 1/f² excess noise spectrum (<100 Hz) superimposed upon 1/f noise in partially depleted (PD) floating body SOI CMOS when devices are biased in the pre-kink region (before the dc kink onset voltage). While the impact ionization phenomenon is negligible in the pre-kink region, the new observed pre-kink excess noise provides a new insight into the body voltage instability and current fluctuation in the SOI CMOSFET     

Empirical correlation between AC kink and low-frequency noiseovershoot in SOI MOSFETs

Low-frequency (LF) noise overshoot has been empirically correlated with the frequency dependence of the kink effect in floating body SOI MOSFETs. Based on the correlation between these unique ac characteristics in SOI, a new mechanism is proposed to explain the well-known kink-related noise overshoot. Also, device solutions for suppressing LF noise overshoot will be discussed     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

AC floating body effects in partially depleted floating body SOInMOS operated at elevated temperature: an analog circuitprospective

AC floating body effects in PD SOI nMOSFETs operated at high temperature are investigated. Both source/body and drain/body junction diode characteristics are greatly influenced by temperature, significantly impacting the ac kink effect as well its low-frequency (LF) noise characteristics. This is especially true for the pre-dc kink operation at high temperature. The increase of junction thermal generation current becomes an important body charging source and induces the LF Lorentzian-like excess noise     

Comparative study of fully depleted and body-grounded non fullydepleted SOI MOSFETs for high performance analog and mixed signalcircuits

This paper compared the performance of conventional fully depleted (FD) SOI MOSFETs and body-grounded nonfully depleted (NFD) SOI MOSFETs for analog applications, A new low-barrier body-contact (LBBC) technology has been developed to provide effective body contact. Experimental results show that the NFD MOSFET's with LBBC structure give one order of magnitude higher output resistance, significantly lower flicker noise, improved subthreshold characteristics, and minimal threshold voltage variation compared with conventional FD SOI MOSFETs. The device characteristics of the LBBC MOSFET's are more desirable for fabricating high performance analog or mixed analog/digital CMOS circuits     

The low-frequency noise overshoot in partially depleted n-channelsilicon-on-insulator twin-MOST's

This paper investigates the effect of the so-called twin-MOST structure on the kink-related low-frequency (LF) noise overshoot, which is observed in partially depleted (PD) SOI nMOST's. It is demonstrated that a significant reduction of the noise overshoot amplitude may be achieved in such a configuration, compared with a single transistor having the same effective gate length. The observed reduction is stronger than the one predicted on purely geometrical grounds, indicating that the floating body effects are indeed successfully reduced by this structure     

"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETS

In this paper, evidence will be provided for the existence of a new class of floating body effects, occurring in SOI and bulk MOSFETs in the linear operation regime and called here the linear kink effects (LKEs). It will be shown that for a sufficiently large front-gate voltage V/sub G/, the transconductance g/sub m/ exhibits a second peak, both for n- and p-channel devices. The effect is most pronounced for partially depleted (PD) n-MOSFETs or bulk MOSFETs at cryogenic temperatures. It occurs as well in fully depleted (FD) transistors, with the back-gate preferably biased into accumulation. Associated with the LKE in the drain current, there is a strong increase of the low-frequency noise spectral density S/sub I/. Similar as for the impact-ionization related noise overshoot, it is observed that the nature of the spectrum changes from 1/f-like to Lorentzian in the LKE region. It is finally shown that the switching off transients change their sign from negative to positive for V/sub G on/ above the LKE threshold, giving evidence for the presence of majority carriers in the film during the ON phase.     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

A Novel Body-tied Silicon-On-Insulator(SOI) n-channel Metal-Oxide-Semiconductor Field-Effect Transistor with Grounded Body Electrode

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current (I_DS-V_DS) curves, substrate resistance effect on the I_DS-V_DS curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.     

0.5μm SOI CMOS器件和电路

研究了0.5μm SOI CMOS器件和电路,开发出成套的0.5μm SOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路,其中当工作电压为3V时,0.5μm 101级环振单级延迟为42ps.同时,对部分耗尽SOI器件特性,如“浮体”效应、“kink”效应和反常亚阈值特性进行了讨论.     

Advanced technologies for optimized sub-quarter-micrometer SOI CMOSdevices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

Physical noise modeling of SOI MOSFETs with analysis of theLorentzian component in the low-frequency noise spectrum

The implementation of a general physics-based compact model for noise in silicon-on-insulator (SOI) MOSFETs is described. Good agreement is shown between model-predicted and measured low-frequency (LF) noise spectra. In particular, the behavior of an excess Lorentzian component that dominates the LF noise spectra of SOI MOSFETs is investigated. Shot noise associated with the generation and removal (via recombination or a body contact) of body charge is shown to underlie the behavior of the Lorentzian in both floating-body and body-tied-to-source SOI MOSFET's operating under partially depleted or “mildly” fully depleted conditions; the Lorentzian is suppressed when the body is “strongly” fully depleted. Good physical insight distinguishes the behavior of the Lorentzian components in all these devices, and predicts the occurrence of additional excess noise sources in future scaled technologies. Simple analytic expressions that approximate the full model are derived to provide the insight     

The cryogenic operation of partially depleted silicon-on-insulatorinverters

This paper describes the cryogenic operation of inverters fabricated in a partially depleted (PD) 1 μm Silicon-on-Insulator (SOI) CMOS technology. As is shown, the floating-body effects like the kink effect degrade the static transfer characteristics considerably. Generally, the effects aggravate upon cooling. Additionally, at deep cryogenic temperatures, e.g., 4.2 K, typical low-temperature anomalies, which are related to the device freeze-out, cause hysteresis effects. Ways for improvement are discussed and compared: As is shown, the PD SOT inverter anomalies can be largely reduced by using the so-called twin-gate configuration     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands