Dynamic data retention and implied design criteria forfloating-body SOI DRAM

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications     

A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.     

Numerical analysis of deep-trap behaviors on retention time distribution of DRAMs with negative wordline bias

The data retention time characteristics of the DRAM cell with the negative wordline bias are investigated. With the unique characteristics shown in the gate-induced drain leakage current and the data retention time distribution of the 256-Mb DRAM chip, a model for the sensitivity of data retention time to gate bias is proposed. With the help of two-dimensional device simulation, we found that the relative trap energy (/spl Delta/E/sub t/) of the trap energy to intrinsic Fermi energy plays a key role to determine the retention time of a DRAM cell transistor for the weak cell as well as the normal cell. Also, it is shown the localized trap in the specific region having large electric field is responsible for abnormally large leakage current of the weak cell. An analytic formula for activation energy for the weak cell and the normal cell are also proposed to estimate trap energy level in real device.     

Designed Workfunction Engineering of Double-Stacked Metal Nanocrystals for Nonvolatile Memory Application

A double-stacked nanocrystal (DSNC) flash memory is presented for improvement of both program/erase (P/E) speed and data retention time. Four combinations of nickel (Ni) and gold (Au) (Ni/Ni, Au/Au, Ni/Au, and Au/Ni) are used as charge storage DSNC materials and are compared from the perspective of memory performance. Through experimental results for P/E efficiency and retention time, the optimized energy band lineup for faster P/E and longer charge retention is presented. A combination of a deep potential well at the top and a shallow potential well at the bottom exhibits optimized performance in P/E, and this combination also shows the longest data retention characteristics.      

Nanowire width dependence of data retention and endurance characteristics in nanowire SONOS flash memory

The investigations on the nanowire width (W) dependence of memory performance including P/E (programming and erasing) speed, data retention time and endurance characteristics in nanowire SONOS flash memory have been performed through the measurement and the device simulation. From measured results, a narrow device has advantages in terms of a fast P/E speed and the endurance characteristics. However, a narrow device has disadvantage in terms of the decreased data retention time. Another disadvantage of a narrow device is expected to the large power consumption due to large GIDL (Gate Induced Drain Leakage) current. The device simulation was performed to explore the causes for a fast P/E speed, an enhanced endurance characteristics and the reduced data retention time in narrow devices.     

一种具有掉电数据保持功能的触发器设计

提出了一种用相变器件作为可擦写存储单元的具有掉电数据保持功能的触发器电路.该触发器由四部分组成:具有恢复掉电时数据的双置位端触发器DFF、上电掉电监测置位电路(Power On/Off Reset)、相变存储单元的读写电路(Read Write)和Reset/Set信号产生电路,使之在掉电时能够保存数据,并在上电时完成数据恢复.基于0.13μm SMIC标准CMOS工艺,采用Candence软件对触发器进行仿真,掉电速度达到0.15μs/V的情况下,上电时可以在30ns内恢复掉电时的数据状态.     

Data retention in organic ferroelectric resistive switches

Solution-processed organic ferroelectric resistive switches could become the long-missing non-volatile memory elements in organic electronic devices. To this end, data retention in these devices should be characterized, understood and controlled. First, it is shown that the measurement protocol can strongly affect the ‘apparent’ retention time and a suitable protocol is identified. Second, it is shown by experimental and theoretical methods that partial depolarization of the ferroelectric is the major mechanism responsible for imperfect data retention. This depolarization occurs in close vicinity to the semiconductor-ferroelectric interface, is driven by energy minimization and is inherently present in this type of phase-separated polymer blends. Third, a direct relation between data retention and the charge injection barrier height of the resistive switch is demonstrated experimentally and numerically. Tuning the injection barrier height allows to improve retention by many orders of magnitude in time, albeit at the cost of a reduced on/off ratio.     

Improving the Retention and Endurance Characteristics of Charge-Trapping Memory by Using Double Quantum Barriers

We have studied the performance of double-quantum-barrier [TaN-Ir₃Si]-[HfAlO-LaAlO₃]-Hf_0.3N_0.2O_0.5-[HfAlO-SiO₂]-Si charge-trapping memory devices. These devices display good characteristics in terms of their plusmn9-V program/erase (P/E) voltage, 100-mus P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degC. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.     

FeRAM retention analysis method based on memory cell read signalvoltage measurement

A retention analysis method for ferroelectric random access memory (FeRAM) was developed, in which read signal voltages from memory cells are measured. The method uses on-chip sample/hold circuits, an off-chip A/D converter, and memory large-scale integration testing equipment. FeRAM chip retention lifetime can be estimated on the basis of FeRAM read signal voltages after retention periods of one day and upwards. When used as a tool to estimate long-term data retention in FeRAM chips and to analyze fluctuations in memory cell characteristics, this method can provide useful information about FeRAM reliability     

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.     

Prediction of data retention time distribution of DRAM by physics-based statistical Simulation

We have developed a comprehensive TCAD framework that can predict the data retention time distribution of a dynamic random access memory (DRAM) chip using the information about the designed cell transistor by coupled physics-based device and statistical simulations. We estimate the cumulative distribution function of the retention time by calculating the leakage currents of a large number of DRAM cells generated by the Monte Carlo methods. The cells have different configurations in the number, locations, and energy levels of the traps that act as localized leakage sources by the extended Shockley-Read-Hall process that includes the trap-assisted tunneling and the stress-induced bandgap narrowing effects. The linear response in the leakage current of each cell to these leakage sources is obtained through the Green's function methods. As an application, we calculate the retention time distribution of a 128-Mb DRAM chip with the 0.18-/spl mu/m ground rule, and verify that the simulation results agree well with the experimental data. We also study the dependence of the retention time distribution on the temperature and negative wordline bias, and discuss the impact of the gate-induced drain leakage on the tail part of the distribution.     

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.     

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm² and a performance of 34 ns access time     

A circuit technology for a self-refresh 16 Mb DRAM with less than0.5 μA/MB data-retention current

A 16M self-refresh DRAM achieving less than 0.5 μA per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V_BB pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 μA per megabyte. Furthermore, the addition of a gate-received V_BB detector (GRD) reduces dc retention current to less than 0.1 μA per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery     

EEPROM耐久和数据保持试验方法标准分析

介绍了存储器分类,论述非易失性存储器编程机理以及编程/擦除耐久和数据保持试验方法,分析了MIL-STD-883B中的《耐久寿命试验》和JESD22-A117《电可擦除可编程只读存储器(EEPROM)编程/擦除耐久和数据保持应力试验》等试验方法标准.     

A 4-Mb pseudo SRAM operating at 2.6±1 V with 3-μA dataretention current

A 4-Mb pseudo static RAM (PSRAM) suitable for universal battery usage is described. The wide voltage range, 2.6±1 V, is set to target the power supply voltage of the PSRAM considering various voltage levels and charging-discharging characteristics of batteries. A double-to-single automatically switchable booster is developed to provide the wide voltage range operation. To reduce the power dissipation of data retention for battery usage a low-power back-bias generator with a new substrate-level sensor and a temperature-dependent self-refresh timer with a unique internal refresh control scheme are demonstrated. A PSRAM operation ranging from 1 V to more than 5 V was obtained and a 3-μA data retention current was realized at room temperature in contrast with 7 μA at 70°C and V_cc of 2.6 V. This PSRAM allows a 20-Mbyte RAM disk to retain data for two months with a single lithium battery     

Characterization of process-induced mobile ions on the data retention in flash memory

Data retention is a major issue that significantly affects the reliability of nonvolatile memory. In this paper, data retention behaviors due to mobile ions are extensively characterized by using several test methods. The source of mobile ions during the sputtering of Ti/TiN layers for forming salicide inside array was identified by secondary ion mass spectroscopy (SIMS) analysis. Different test sequences clearly reveal the data retention caused by mobile ions. Salicide block material that includes silicon nitride effectively blocks the impact of mobile ions. Bitmapping patterns on an array indicate that the amount of charge loss spatially depends on its neighbor's high-V/sub th/ cells via the Coulomb's r-square field. The spatial effects of neighboring cells on the charge loss are then estimated. Beyond 1.98 /spl mu/m, the charge loss caused by mobile ions of a individual cell becomes unaffected by the V/sub th/ state of its neighboring cells. Plasma charging cells also attract mobile ions. A considerable charge gain, by as much as 0.8 V with a radial distribution on fresh wafer, was observed after a UV-bake test. The interaction between plasma charging effect and mobile ions movement during wafer processing explains this interesting feature.     

A Program-Erasable High-κ Hf0.3N0.2O0.5 MIS Capacitor With Good Retention

We describe a programmable-erasable MIS capacitor with a single high-k Hf_0.3N_0.2O_0.5 dielectric layer. This device showed a capacitance density of ~6.6 fF/mum², low program and erase voltages of +5 and -5 V, respectively, and a large DeltaV_fb memory window of 1.5 V. In addition, the 25degC data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf_0.3N_0.2O_0.5.     

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

EEPROM单元的电荷保持特性

利用理论推导和实验方法对电可擦除可编程只读存储器EEPROM单元在给定电压下的电荷保持特性进行了分析和研究,得出了EEPROM单元电荷保持能力的理论公式,得到了单元保持状态下的电特性曲线,发现在双对数坐标下,阈值电压的退化率与时间成线性关系.在假定电荷流失机制为Fowler-Nordheim隧穿效应的情况下,推出了EEPROM单元在给定外加电压下的电荷保持时间,并通过实验得出了简化的EEPROM单元寿命公式.