一种单片集成光电检测电路前置放大器的噪声性能分析与优化

在光电检测电路中虽然前置放大器的增益可以做到足够大,但是在弱信号被放大的同时,噪声也被放大,而且放大器本身还要引入新的噪声。为使探测系统保持一定的输出信噪比,合理设计前置放大器噪声性能是十分重要的。对单片集成光电检测电路中的各种噪声来源与形成机制进行分析,结合计算机仿真探索优化前置放大器噪声性能的设计方法。     

高灵敏度测氡脉冲电离室前置放大器设计

针对主流的商用测氡仪器在测量低浓度氡时精度低的问题,基于新型离子脉冲电离室输出信号特点,设计了一种基于集成运算放大器TL071的高灵敏前置放大电路.该前置放大器由电流电压转换、放大电路以及时间常数相同的CR-RC积分、微分滤波成形电路构成.使用Multisim10对其增益、幅频特性、失真度、信噪比以及输入阻抗等性能进行仿真与测试,结果表明:此前置放大器能将pA级的电流信号转换为电压信号并放大到V级,输入阻抗约为105 MΩ,电路失真度理论值可以达到O％,信噪比可达到100 dB.     

激波压力传感器信号处理电路设计

针对声学靶装置中采用的一种激波传感器．设计了相应的传感器输出信号转换、处理电路,该信号处理电路由电荷放大电路和滤波电路组成。采用运算放大器OPA604设计了电荷放大电路,信号滤波电路采用集成有源滤波器UAF42进行设计。经实弹测试验证,利用该信号处理电路,得到了较好的弹丸激波压力波形。     

电荷放大器校准的研究

本文介绍了电荷放大器的基本工作原理和使用方式,对电荷放大器的性能进行了介绍,它将传感器输出的微弱电荷信号转化为放大的电压信号,同时又能将传感器的高阻抗输出转换成低阻抗输出,根据新的检定规程,本文探讨了对各类电荷放大器进行校准的方法,分析了用模块化设计实现自动化校准,为有效开展电荷放大器自动校准提出了切实可行的建议。     

集成运算放大器的误差分析

集成运算放大器是在放大电路中主要使用的电子元件,随着技术的不断优化,集成运算放大器较高的可靠性与使用简便渐渐成为了放大电路重要电子元件的不二选择。集成运算放大器性能不佳的时候,会引起运算的误差,这些误差直接影响了集成运算放大器的工作性能,不利于放大电路的工作计算。     

压电加速度传感器输出信号可变增益控制

针对压电加速度传感器信号调理电路中标定过程繁琐、标定效率低下、系统在运行过程中输出信号增益不能改变的问题,提出了在电荷放大器之后由微控制器控制数字电位器组成可调增益的电压放大电路,实现加速度计输出信号的自动标定和增益的可变控制.分析压电式加速度计的信号调理电路,在电压放大电路中选择使用数字电位器的方法实现可变增益控制,...     

电荷放大器可靠性分析

介绍了电荷放大器在存储测试系统中的作用,详细说明了电荷放大器工作原理,推导出电荷量与输出电压之间的关系。通过故障树的方法对电荷放大器的可靠性进行分析,得出电荷放大器的MTBF和可靠性曲线,定量计算出电阻、电容、焊点和芯片在一个完整的存储测试电路中的失效率,定性的分析出不同部分对整体系统失效率的影响度。     

小功率音频放大电路的设计及PSPICE仿真

系统介绍分立小功率音频放大电路的一般设计方法及过程,并用ORCAD_PSPICE仿真软件对设计的电路进行静态、瞬态、DCSWEEP、ACSWEEP等仿真分析,不断提高整个电路的性能,以满足设计要求。     

小型地磁传感器的低噪声前置放大电路设计

一些小型地磁传感器输出噪声电压水平在10 nV/Hz左右,现有nV级噪声水平的前置放大器体积太大难以满足其信号调理需求.针对这个问题,本文阐述了低噪声放大电路输入级设计原理,利用Multisim对输入级电路等效输入噪声电压等指标进行仿真,研制出一种基于差分输入的小型低噪声前置放大电路.给出了电路关键性能指标的仿真和测试结果,测试结果表明该电路具有良好的噪声特性和共模抑制比,噪声电压水平仅为3.7 nV/(Hz)～(1/2)@3.5 kHz,共模抑制比110 dB,增益为100～1 000连续可调.     

基于双电荷放大器的数字式两线制HART涡街流量变送器

针对耐高温涡街流量传感器灵敏度低及引入HART通信增加数字式两线制仪表的功耗且通信稳定性容易受电源影响的问题,研制了基于双电荷放大器的数字式两线制HART涡街流量变送器。采用两级电荷放大器和两级低通滤波器的信号调理电路,对耐高温涡街流量传感器输出的幅值较小的信号进行放大和滤波,获得稳定的流量信号;采用两路隔离电源的电源设计方案,提高电源的负载能力,并保证通信的稳定性,在进行数字信号处理的同时,实现两线制HART通信。实验结果表明,该变送器测量精度较高、量程下限较低,且满足低功耗要求。     

A Simple Stray-Free Capacitance Meter by Using an Operational Amplifier

A simple operational amplifier circuit known as a charge amplifier has an advantage of measuring capacitance independent of stray capacitance. Capacitance down to 0.03 pF could be experimentally measured with ease and the theoretical limit of measurement is discussed. Also the direct measurement of the electrostatic induction coefficients of a system of conductors by the circuit is introduced.     

二元并行CdZnTe探测器读出电路及信号处理方法

本文为CdznTe(CZT)二元并行探测器设计并制作了信号处理系统电路,包括前置放大电路,差分放大电路,极零相消电路,滤波成形电路,微调电路和基线恢复电路和加和电路.137Cs(662keV)辐射下的信号,经过差分放大,极零相消和滤波成形电路的输出,信号持续时间在10μs内,幅度为260mV,两路信号相加后信噪比大于15:1.能谱测试初步结果表明:采用这个信号处理系统,二元CZT并行探测器对137Cs(662keV)源的探测效率分别是单元器件的1.74和2.2倍,能量分辨率接近于单元器件.     

175$^circhboxC$Silicon-Based Hybrid Charge Amplifier for 175$^circhboxC$and 100-mV/G Miniature Piezoelectric Accelerometer

High-temperature hybrid miniature silicon-based charge amplifier has been designed, fabricated, and tested. The charge gain$G_q approx 30 hboxmV/pC pm 1 hboxdB$at the reference frequency of 100 Hz. Frequency response deviation is$pm$1 dB at frequency range from about 0.5 Hz to about 10 kHz over the temperature range from$-55 ^circhboxC$to$175 ^circhboxC$. The maximum change in gain is$pm$5% over that temperature range. The maximum output signal is 5 V peak at voltage supply of$+$24 V. The charge amplifier compromises standard components, and it is built on the ceramic disk substrate with a diameter of about 8 mm. This circuit made possible the development of the industry's first 100-mV/G miniature (cube with side of 14 mm), lightweight (12.5 g), low-cost, and low-noise piezoelectric triaxial accelerometer with integral silicon-based electronics having operating temperature from$-55 ^circhboxC$to$175 ^circhboxC$. In the long-term active (with power supply) test, the circuit and the accelerometer operated at temperature of 175$^circhboxC$for 1000 h without any signs of degradation.     

Using SQUIDs to Detect Charge in Cryogenic Germanium Detectors

This paper describes an impedance matching network which allows charge impulses to be measured by a SQUID amplifier with an RMS charge noise of less than 100?e, assuming the SQUID amplifier has a current noise of 2? $\mathrm{pA}/\sqrt{\mathrm{Hz}}$ , and the current pulse has a duration of about 1?μs or shorter. The component values are provided for an example system which has an RMS charge noise of 91?e, assuming all dissipative circuit elements are cooled to a temperature of 100?mK.     

The maximal area of superconducting tunneling junction x-ray detectors determined by the required signal-to-noise ratio

The intrinsically high energy resolution of superconducting tunneling junctions (STJ) requires a low noise charge sensitive amplifier circuit. The noise sources of such a junction + amplifier circuit are discussed. The dominant noise sources are the series noise and the flicker noise of the FET input stage, amplified by the large input capacitance of the STJ-detector. Means to reduce this capacitance are discussed. Reducing the preamplifier noise by a factor of two and the height of the potential barrier of the insulating layer by two orders of magnitude, by keeping the large conductance of the junction constant, would allow an increase in junction area by a factor of 15.     

Cache Memory Design for Single Bit Architecture with Different SenseAmplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.     

低噪声电容式MEMS加速度计接口专用集成电路设计

为了提高MEMS电容式加速度计的检测分辨率,降低系统噪声,提出了一种改进的基于开关电容的闭环检测电路.该电路采用新型的电荷积分器实现电容-电压转换,对寄生电容不敏感,具有非常低的噪声,同时,降低了由于运放的有限带宽、有限增益以及失调造成的影响.采用相关双采样（CDS）技术进一步消除了1/f噪声和电路中的失调.同时为了精确模拟传感器的结构部分,对结构的等效电学模型进行了改进,引入两个压控电流源,分别由互为反相的两个时钟信号控制,消除了运放失调、噪声等非理想因素产生的误差.实验制作了ASIC芯片与传感器结构的双片集成微加速度计,芯片采用0.5μmCMOS工艺流片,系统测试结果表明该闭环加速度计的灵敏度为620mV/g,非线性度为0.126%,噪声密度为24μg.Hz-21,整体功耗为30mW.     

Implementation of a charge-based neural Euclidean classifier for a3-bit flash analog-to-digital converter

This paper describes the implementation of a Euclidean squared classifier with a charge based synaptic matrix and discriminator, based on a previously implemented Hamming classifier. The discriminator circuit is a generalized n-port version of the two-port differential charge-sensing amplifier that is conventionally used in DRAM's for bitline sensing. Both the quantifier and discriminator are implemented by charge based techniques, granting the simultaneous availability of high integration density, low power consumption, and high speed. The analog-to-digital (A/D) implementation was chosen to illustrate the network's classification characteristics, since A/D conversion can be interpreted as classifying an input in terms of A/D quantization levels. A detailed analysis of the classifier configuration is presented. Design issues are addressed at both the system and circuit levels, and some limitations are identified. Both simulation results and measurements of the implemented chip are presented to confirm the theoretical analysis. The circuit occupies an area of 500 μm×250 μm, operates with a single 5 V power supply, and consumes less than 1 mW of static power     

A Multispectral Analog Photon-Counting Readout Circuit for X-ray Hybrid Pixel Detectors

In this paper, an all-analog pixel architecture for the readout of X-ray pixel detectors with multiple energy discrimination is proposed. The circuit comprises a self-triggered reset charge amplifier and three distinct channels devoted to the detection on a specific energy band. Each channel is composed of an autocalibrated comparator, an energy window identification logic, and an analog counter with an adjustable dynamic range. A test prototype has been implemented with a standard complementary metal-oxide-semiconductor 0.35-mum technology. The pixel circuitry dissipates 15 muW at 3.3 V, has a noise equivalent charge of 82 e_rms ^- at 200 fF, and allows, on each of the three channels, a dynamic range that exceeds 12 bits. The designed pixel is a square with a 109-mum pitch.