字节式单向错误纠错码

介绍了一种有效的字节式单向错误纠错码及其编码和译码算法。从对校验位数下限值的讨论可以看出,这里介绍的码优于字节式对称错误纠错码,并且近似最优。本文还介绍了字节式非对称错误纠错码。     

基于CycloneⅢ构成的RS编码系统

本文采用Altera公司的FPGA器件Cyclone Ⅲ系列EP3C10作为核心器件构成了R-S(255,223)编码系统;利用Quartus Ⅱ 9.0作为硬件仿真平台,用硬件描述语言Verilog_HDL实现编程,并且通过JTAG接口与EP3C10连接。R-S(Reed-Solomon)码是一类纠错能力很强的特殊的非二进制BCH码,能应对随机性和突发性错误,广泛应用于各种通信系统中和保密系统中。R-S(255,223)码能够检测32字节长度和纠错16字节长度的连续数据错误信息。     

直升机卫星通信系统中Turbo码外交织器设计与仿真

在直升机卫星通信系统(HSCS)中,如何克服由于旋翼遮挡导致的系统性能恶化是一个亟需解决的关键问题。旋翼遮挡相当于对码字信息的成片删除,通过分析删余Turbo码中删余矩阵的设计准则,首先对Turbo码的编码结构进行改进,并提出了一种适用于直升机旋翼遮挡环境下的交织器。它满足以下特性:将删除均匀分散在整个码字序列中,变突发错误为随机错误;码字中每个信息位与其对应的2比特校验位中最多只删1位;与被删比特组相邻的两个比特组保留;删除部分中以信息位-校验位1-校验位2的模式循环,这些特性保证了删除信息的可靠恢复。最后对不同遮挡比例下新型交织器与传统交织器进行仿真比较,结果表明采用新型交织器改善了数据传输的误码率(BER)性能,提高了HSCS系统的可靠性。     

部分系统Turbo码的研究

对一种码率为1／2的部分系统turbo码性能进行了讨论。它是通过对码率为1／3的turbo码的校验位和信息位进行删余得到的。这种码的“误码下限”（error-floor）比对应的系统码要低。因此,码率为1／2的turbo码,在没有增加编码和译码复杂性的情况下,通过简单地对信息位和校验位的删除可以提高性能。     

一类性能好、复杂度低的纠错编码--乘加码

对一类性能好且复杂度低的纠错编码技术——乘加码进行了介绍。他是在单校验位的Turbo乘积码(Single Parity Check Turbo Product Code)的基础上改进而来的,即由单校验位的Turbo乘积码作为外码,码率为1的递归卷积码作为内码串行级联而成。介绍了乘加码的编码方式和译码方法,并给出了其性能分析。对于一定的分组长度,这类码表现出与Turbo码相近的性能,但其译码复杂度要远远低于Turbo码。     

浅谈波分设备误码处理

误码是指在传输过程中码元发生了错误，错误通常以bit位来表示。在SDH帧结构中，用于误码检测的字节是B1、B2、M1、B3、G1、V5。但在波分设备中，OTU单板只对B1、B2字节进行监测。     

容错256K存贮器的设计

报导了一系列256k存贮器的设计,它们都将错误校正编码集成进存贮器结构中去。从简单的单一错误校正乘积码起,成功的设计在编码能力、存取延迟及通讯和计算的复杂性方面寻找折衷方案。在最有效的设计中,所有256k位被编制形成一个代码字,这是从一个摄影平面导出的双重错误校正和三重错误检测码。因为所有的位都是这个单一代码字的元素,所以编码效能很高,所需要的奇偶校验位仪增加了存贮容量的大约百分之三。单一的错误校正可以在读的时候进行,而只比通常无冗余的存贮器附加很少延迟时间。多个错误校正可以由存储器管理系统来进行。各种失效模式,包括组成64×64子矩阵之一的整个一列失效也是可以容许的。写入存储器包括一个读写周期,比般的存储器稍微慢一点。     

一种快速的防伪起始码处理方法

伪起始码在AVS视频编码标准中起着关键作用.出现伪起始码将使图像的头信息发生错误,导致后续信息发生错位.因此,在完成熵编码输出前,必须进行伪起始码检测.分析了传统的和AVS标准中采用的防伪起码方法,在此基础上,提出了一种采用整字节检测的快速防伪起始码方法.实验结果表明,相对于原有方法,在有无伪起始码时,处理速度均可提高20倍以上.     

基于一种交织码的多位翻转容错技术研究

随着技术的发展和核心电压的降低,存储器更易受瞬时错误（软错误）影响,成为影响航天器件可靠性的主要原因。错误检测与纠正（EDAC）码（也称错误纠正码）常用来对SRAM型存储器中的瞬时错误进行纠正,由单个高能粒子引起的多位翻转错误（SEMU）是普通纠一检二（SEC-DED）编码所无法处理的。提出了一种交织度为2的(26,16)交织码,该码由两个能纠正一位随机错误、二位突发错误的(13,8)系统码组成,(26,16)交织码能够纠正单个码字中小于二位的随机错误和小于四位突发错误（DEC-QAEC）。通过理论分析和硬件平台实验表明,该交织码在存储资源占用率、实时性相当情况下可靠性优于同等长度的SEC DED码,能有效提高SRAM型存储器抗多位翻转错误的能力。      

利用循环码生成多项式导出的CRC校验码计算程序

文中在简单地讨论了循环码基本特性的基础上，导出了一个利用程序计算循环系统码的校验位的流程。按照导出的流程用ＱＡＢＡＳＩＣ语言编制了一个通用的ＣＲＣ校验码编码的计算程序。利用给出的程序，可方便地计算出任决给定的码生成多项式ｇ（ｘ）及信息序列对庆的系统码的ＣＲＣ校验位。     

The Design of a High-Performance Error-Correcting Coding Scheme for the Canadian Broadcast Telidon System Based on Reed-Solomon Codes

Error correction can greatly improve the performance and extend the range of broadcast teletext systems. In this paper, the requirements for an error-correcting scheme for broadcast teletext in North America (NABTS) are set down. An error-correction scheme which meets all these requirements is then described. The simplest case employs the one parity bit in each 8 bit byte and no suffix of parity check bits at the end of each data block. The next level also uses a single byte of parity check bits at the end of each data block. Adding a second byte of parity checks at the end of each data block results in a Reed-Solomon code, called theCcode, for each data block. Adding one data block of parity checks afterh - 1data blocks results in a set ofhdata packets being encoded into a bundle, in which verticalCcodes provide powerful interleaving. In a final alternative, two data blocks hold the check bytes for the vertical codewords, and the most powerful coding scheme, the double bundle code, results. The detailed mathematical definitions of the various codes are referred to or described, formulas for performance calculations are referred to, and performance curves are presented for the AWGN channel as well as for measured field data. These performance curves are discussed and compared to the performance of a difference set cyclic code, originally designed for the Japanese teletext system, which corrects any 8 bits in error in a packet.     

A 50-ns CMOS 256 K EEPROM

A 32 K×8 EEPROM (electrically erasable programmable read-only memory), which operates with a single 5-V power supply and achieves 100 K cycle endurance, 50-ns typical read access time, and 1-ms page programming time, equivalent to 16 μs/byte, was designed. A double-poly, double-metal, n-well CMOS process with 1.25-μm minimum feature size was developed to manufacture the device. The required and optional extended JEDEC standards for software data protection and chip clear are implemented along with parity check, toggle bit, page-load timer, and data-protection status bit. A modified Hamming code, which uses four parity bits per byte, was implemented to detect and correct single-bit errors     

Effects of LDPC Code on the BER Performance of MPSK System with Imperfect Receiver Components over Rician Channels

In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low‐density parity‐check coded multilevel phase‐shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in‐phase‐quadrature mismatch, and the fading severity.     

A Class of High Rate Codes for Byte-Oriented Information Systems

In this paper we introduce a class of linear codes especially designed to provide additional error protection for data consisting of bytes all having even (or odd) parity (e.g., ASCII characters). The technique consists in adding an overall parity byte computed as a linear function of the information bytes. The linear function is designed such that the resulting codes can correct all single errors and all double errors occurring in distinct information bytes. It is shown that any code which can correct these latter mentioned error patterns has an overall length of at most 37 bytes, and a specific code of length 29 bytes is described. A practical decoding algorithm for the new class of codes is described. Finally, the performance of the codes, when used on the binary symmetric channel, is compared with that of the row-column codes for which the additional parity byte is simply the modulo-2 sum of the information bytes.     

An error-correcting coding scheme for teletext and othertransparent data broadcasting

Nonprimitive and primitive Reed-Solomon (RS) codes (and product codes based on them) that can provide a very low bit error rate (BER) for the transparent data broadcasting feature of North American broadcast Teletext Specification (NABTS) are described. Transparent data consist of 8-b bytes, each without a parity-check bit, as contrasted with nontransparent data, which consist of 8 bit bytes, each of which has a parity-check bit in every byte. Specific applications for transparent error-coding codes constructed from RS codes in broadcast teletext broadcasting are discussed. Nonprimitive RS codes designed for nontransparent data broadcasting by NABTS teletext are derived, and powerful product forms of shortened nonprimitive Reed-Solomon codes are described     

Construction techniques for systematic SEC-DED codes with singlebyte error detection and partial correction capability for computermemory systems

Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per byte     

An STS-N byte-interleaving multiplexer/scrambler anddemultiplexer/descrambler architecture and its experimental OC-48implementation

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10^-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

Turbo Receiver for Multicarrier Spread Spectrum Systems Employing Parity Bit Selected Spreading Sequences

In this paper a turbo receiver for multicarrier spread spectrum systems employing parity bit selected spreading code (MC-SS-PB) is proposed where detection and decoding are performed iteratively for each detected bit in the receiver. In MC-SS-PB systems, the parity bits generated by a linear block encoder are used to select a spreading code from a set of orthogonal spreading sequences. The selected spreading code is then used to spread the signals in all subcarriers. In the proposed receiver, soft information passes between the detector and the decoder on multiple iterations. Detection is performed by using the received signal in combination with the extrinsic likelihood provided by a soft input soft output decoder. The turbo receiver is further extended to a multiple user system where the multiple access interference is estimated in each iteration and subtracted out from the received signal. Simulations show a significant reduction in bit error rates when a turbo receiver is used in these systems.     

高性能差错控制编码的硬件设计与实现

为提高航天测控通信系统中数据传输的可靠性、确保终端接收数据的正确性,需对被传输的测控数据进行高速差错编码。基于循环冗余校验编码,在硬件电路中设计并实现了一种简单高效的差错编码方式。首先将被传输的数据按照一定字节进行分帧,每帧数据加入特定的帧头,每帧数据按字节进行八比特差错编码,差错编码按照查表方式进行。对每帧数据的差错编码值再进行一比特纠错编码。实验仿真结果表明所设计的差错编码具有性能高、硬件资源消耗低和编码速度快等特点,适合于高速大容量数据可靠性传输。