Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm²/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10⁴. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.     

Chitosan-gated low-voltage transparent indium-free aluminum-doped zinc oxide thin-film transistors

Low-voltage transparent indium-free aluminum-doped zinc oxide (AZO) thin-film transistors (TFTs) are demonstrated by using chitosan polymer electrolyte as the gate dielectric. Chitosan with a large specific capacitance (0.4 μF/cm²) is obtained possibly due to the strong electric-double-layer (EDL) effect through the mobile-proton hopping mechanism. Herein, low-cost indium-free AZO film is developed for replacing the traditional ITO/IZO electrodes. A simple method is developed to fabricate all of the channel and source/drain electrodes during one-step sputter process by using such a low-cost indium-free AZO film. The optimized TFTs with 30 nm AZO thickness shows the best performance with a low operation voltage of 1.5 V, a large on-off ratio of 10⁵, and a field-effect mobility of 8.3 cm²/Vs, respectively. The chitosan-gated AZO TFTs may provide a good candidate for the applications of next-generation transparent flexible low-cost portable electronics.     

ZnO Thin Film, Device, and Circuit Fabrication using Low-Temperature PECVD Processes

We report undoped ZnO films deposited at low temperature (200°C) using plasma-enhanced chemical vapor deposition (PECVD). ZnO thin-film transistors (TFTs) fabricated using ZnO and Al₂O₃ deposited in situ by PECVD with moderate gate leakage show a field-effect mobility of 10 cm²/V s, threshold voltage of 7.5 V, subthreshold slope <1 V/dec, and current on/off ratios >10⁴. Inverter circuits fabricated using these ZnO TFTs show peak gain magnitude (dV _out/dV _in) ~5. These devices appear to be strongly limited by interface states and reducing the gate leakage results in TFTs with lower mobility. For example, ZnO TFTs fabricated with low-leakage Al₂O₃ have mobility near 0.05 cm²/V s, and five-stage ring-oscillator integrated circuits fabricated using these TFTs have a 1.2 kHz oscillation frequency at 60 V, likely limited by interface states.     

Zinc Oxide Thin-Film Transistors Fabricated at Low Temperature by Chemical Spray Pyrolysis

We report the electrical behavior of undoped zinc oxide thin-film transistors (TFTs) fabricated by low-temperature chemical spray pyrolysis. An aerosol system utilizing aerodynamic focusing was used to deposit the ZnO. Polycrystalline films were subsequently formed by annealing at the relatively low temperature of 140°C. The saturation mobility of the TFTs was 2 cm²/Vs, which is the highest reported for undoped ZnO TFTs manufactured below 150°C. The devices also had an on/off ratio of 10⁴ and a threshold voltage of ?3.5 V. These values were found to depend reversibly on measurement conditions.     

High air stability of threshold voltage on gate bias stress in pentacene TFTs with a hydroxyl-free and amorphous fluoropolymer as gate insulators

We investigated the air stabilities of threshold voltages (V_th) on gate bias stress in pentacene thin-film transistors (TFTs) with a hydroxyl-free and amorphous fluoropolymer as gate insulators. The 40-nm-thick thin films of spin-coated fluoropolymer had excellent electrical insulating properties, and the pentacene TFTs exhibited negligible current hysteresis, low leakage current, a field-effect mobility of 0.45 cm²/Vs and an on/off current ratio of 3 × 10⁷ when it was operated at −20 V in ambient air. After a gate bias stress of 10⁴ s, a small V_th shift below 1.1 V was obtained despite non-passivation of the pentacene layer. We have discussed that the excellent air stability of V_th was attributed to the insulator surface without hydroxyl groups.     

High mobility poly-Ge thin-film transistors fabricated on flexible plastic substrates at temperatures below 130°C

Depletion-mode poly-Ge thin-film transistors (TFTs) with an effective hole mobility of 110 cm²/Vs and an ON/OFF ratio of 10⁴ have been fabricated on flexible polyethylene therephtalate (PET) substrates, taking advantage of a novel stress-assisted crystallization technique. Proper manipulation of an otherwise destructive mechanical stress leads to a drastic drop of crystallization temperature from 400°C to 130°C. External compressive stress is transferred to the Ge/PET interface by bending the flexible substrate inward, during the thermal post-treatment. Proper patterning of the a-Ge layer before thermomechanical post-treatment leads to a minimal crack density in the processed poly-Ge layer. Reduction in the crack density plays a crucial role in alleviating the stress-induced gate leakage current emanated from the crack traces propagating from the channel into the gate oxide.     

Impact of Layer Configuration and Doping on Electron Transport and Bias Stability in Heterojunction and Superlattice Metal Oxide Transistors

The astonishing recent progress in the field of metal oxide thin‐film transistors (TFTs) and their debut in commercial displays is accomplished using vacuum‐processed multicomponent oxide semiconductors. However, emulating this success with their solution‐processable counterparts poses numerous scientific challenges. Here, the development of high mobility n‐channel TFTs based on ultrathin (<10 nm) alternating layers of In₂O₃ and ZnO that are sequentially deposited to form heterojunction and superlattice channels is reported. The resulting TFTs exhibit high electron saturation mobility (13 cm² V^?1 s^?1), excellent current on/off ratios (>10⁸) with nearly zero onset voltages and hysteresis‐free operation despite the low temperature processing (≤200 °C). The enhanced performance is attributed to the formation of a quasi‐2D electron gas‐like system at the In₂O₃/ZnO heterointerface due to the conduction band offset. It is shown that altering the oxide deposition sequence has an adverse effect on electron transport due to formation of trap states. Optimized multilayer TFTs are shown to exhibit improved bias‐stress stability compared to single‐layer TFTs. Modulating the electron concentration within the superlattice channel via selective n‐doping of the ZnO interlayers leads to almost 100% saturation mobility increase (≈25 cm² V^?1 s^?1) even when the TFTs are fabricated on flexible plastic substrates.     

Capacitively Coupled Hybrid Ion Gel and Carbon Nanotube Thin‐Film Transistors for Low Voltage Flexible Logic Circuits

The lamination of a high‐capacitance ion gel dielectric layer onto semiconducting carbon nanotube (CNT) thin‐film transistors (TFTs) that are bottom‐gated with a low‐capacitance polymer dielectric layer drastically reduces the operating voltage of the devices resulting from the capacitive coupling effect between the two dielectric layers sandwiching the CNT channel. As the CNT channel has a network structure, only a compact area of ion gel is required to make the capacitive coupling effect viable, unlike the planar channels of previously reported transistors that required a substantially larger area of ion gel dielectric layer to induce the coupling effect. The capacitively coupled CNT TFTs possess superlative electrical characteristics such as high carrier mobilities (42.0 cm² (Vs)^?1 for holes and 59.1 cm² (Vs)^?1 for electrons), steep subthreshold swings (160 mV dec^?1 for holes and 100 mV dec^?1 for electrons), and low gate leakage currents (<1 nA). These devices can be further integrated to form complex logic circuits on flexible substrates with high mechanical resilience. The layered geometry of the device coupled with scalable solution‐based fabrication has significant potential for large‐scale flexible electronics.     

Printable Organic‐Inorganic Nanoscale Multilayer Gate Dielectrics for Thin‐Film Transistors Enabled by a Polymeric Organic Interlayer

Here, a new approach to the layer‐by‐layer solution‐processed fabrication of organic/inorganic hybrid self‐assembled nanodielectrics (SANDs) is reported and it is demonstrated that these ultrathin gate dielectric films can be printed. The organic SAND component, named P‐PAE, consists of polarizable π‐electron phosphonic acid‐based units bound to a polymeric backbone. Thus, the new polymeric SAND (PSAND) can be fabricated either by spin‐coating or blade‐coating in air, by alternating P‐PAE, a capping reagent layer, and an ultrathin ZrOx layer. The new PSANDs thickness vary from 6 to 15 nm depending on the number of organic‐ZrOx bilayers, exhibit tunable film thickness, well‐defined nanostructures, large electrical capacitance (up to 558 nF cm^?2), and good insulating properties (leakage current densities as low as 10^?6 A cm^?2). Organic thin‐film transistors that are fabricated with representative p‐/n‐type organic molecular/polymeric semiconducting materials, function well at low voltages (<3.0 V). Furthermore, flexible TFTs fabricated with PSAND exhibit excellent mechanical flexibility and good stress stability, offering a promising route to low operating voltage flexible electronics. Finally, printable PSANDs are also demonstrated and afford TFTs with electrical properties comparable to those achieved with the spin‐coated PSAND‐based devices.     

Inkjet printed thin and uniform dielectrics for capacitors and organic thin film transistors enabled by the coffee ring effect

The deposition of a thin and uniform dielectric layer is required for high performance printed capacitors and thin film transistors (TFTs), however this is difficult to achieve with printing methods. We have demonstrated inkjet-printed dielectrics with a uniform thickness from 70 nm to 200 nm by taking advantage of the coffee ring effect. A high capacitance per unit area of 230 pF/mm² is achieved from capacitors with linear morphologies fully printed onto flexible substrates. We also demonstrate organic TFTs with an average mobility of 0.86 cm²/Vs and a source drain current of 57 μA obtained with a supply voltage of 15 V. This performance was shown to be consistent, with a standard deviation of 15% obtained from hundreds of printed organic TFTs on PET substrates. This consistency was further validated by the production of functional NAND, NOR, AND and OR logic gates. Our results demonstrate that the coffee ring effect, which is usually viewed as undesirable, can enable higher performance in printed electronic devices.     

High Mobility and Stability of Thin-Film Transistors Using Silicon-Doped Amorphous Indium Tin Oxide Semiconductors

We report the fabrication of high-performance thin-film transistors (TFTs) with an amorphous silicon indium tin oxide (a-SITO) channel, which was deposited by cosputtering a silicon dioxide and an indium tin oxide target. The effect of the silicon doping on the device performance and stability of the a-SITO TFTs was investigated. The field-effect mobility and stability under positive bias stress of the a-SITO TFTs with optimized Si content (0.22 at.% Si) dramatically improved to 28.7 cm²/Vs and 1.5 V shift of threshold voltage, respectively, compared with the values (0.72 cm²/Vs and 8.9 V shift) for a-SITO TFTs with 4.22 at.% Si. The role of silicon in a-SITO TFTs is discussed based on various physical and chemical analyses, including x-ray absorption spectroscopy, x-ray photoelectron spectroscopy, and spectroscopic ellipsometry measurements.     

High‐Performance Amorphous Multilayered ZnO‐SnO2 Heterostructure Thin‐Film Transistors: Fabrication and Characteristics

Multilayered ZnO‐SnO₂ heterostructure thin films consisting of ZnO and SnO₂ layers are produced by alternating the pulsed laser ablation of ZnO and SnO₂ targets, and their structural and field‐effect electronic transport properties are investigated as a function of the thickness of the ZnO and SnO₂ layers. The performance parameters of amorphous multilayered ZnO‐SnO₂ heterostructure thin‐film transistors (TFTs) are highly dependent on the thickness of the ZnO and SnO₂ layers. A highest electron mobility of 43 cm²/V·s, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on‐to‐off ratio of 10¹⁰ are obtained for the amorphous multilayered ZnO(1.5 nm)‐SnO₂(1.5 nm) heterostructure TFTs, which is adequate for the operation of next‐generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO‐SnO₂ heterostructure film consisting of ZnO, SnO₂, and ZnO‐SnO₂ interface layers.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

ZnO TFT Devices Built on Glass Substrates

ZnO thin-film transistors (TFTs) were built on glass substrates. The device with a top gate configuration operates in the depletion mode. The ZnO channel was grown by metalorganic chemical vapor deposition (MOCVD) on glass at low temperature. SiO₂ was used as the gate dielectric. The TFT has an on/off ratio of ∼4.0 × 10⁴ and a channel field-effect mobility of ∼4.0 cm²/V s. The average transmittance of the ZnO film in the visible wavelength is ∼80%. To compare the characteristics of the TFTs prepared by using a poly-ZnO and epitaxial-ZnO channel, an epi-ZnO TFT with the same configuration and dimensions was made on an r-Al₂O₃ substrate. The epi-ZnO TFT shows higher field-effect mobility of ∼35 cm²/V s and on/off ratio of ∼10⁸.     

Low-voltage organic transistors with steep subthreshold slope fabricated on commercially available paper

Organic thin-film transistors were fabricated directly on the surface of commercially available cleanroom paper using the vacuum-deposited small-molecule semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT). A thin, high-capacitance gate dielectric that allows the TFTs to be operated with low voltages of 2 V was employed. The TFTs have a charge-carrier mobility of 1.6 cm²/Vs, an on/off current ratio of 10⁶, and a subthreshold slope of 90 mV/decade. In addition, the TFTs also display a very large differential output resistance, which is an important requirement for applications in analog circuits and active-matrix displays.     

Effect of gate insulator thickness on device performance of InGaZnO thin-film transistors

Top-contact thin-film transistors (TFTs) are fabricated in this work using atomic layer deposition (ALD) Al₂O₃ as the gate insulator and radio frequency sputtering InGaZnO (IGZO) as the channel layer so as to investigate the effect of Al₂O₃ thickness on the performance of IGZO-TFTs. The results show that TFT with 100-nm-thick Al₂O₃ (100 nm-Al₂O₃-TFT) exhibits the best electrical performance; specifically, field-effect mobility of 5 cm²/Vs, threshold voltage of 0.95 V, I_on/I_off ratio of 1.1×10⁷ and sub-threshold swing of 0.3 V/dec. The 100 nm-Al₂O₃-TFT also shows a substantially smaller threshold voltage shift of 1.1 V after a 10 V gate voltage is applied for 1 h, while the values for TFTs with an Al₂O₃ thickness of 220 and 280 nm are 1.84 and 2 V, respectively. The best performance of 100 nm-Al₂O₃-TFT can be attributed to the larger capacitance and the smaller amount of total trap centers possessed by a thinner insulator compared to the thicker ones.     

Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates

High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

N-channel thin-film transistors constructed on plastic by solution processes of HgSe nanocrystals

We demonstrate bottom-gate thin-film transistors (TFTs) based on solution-processed HgSe nanocrystals (NCs) on plastic substrates. Solid films made of spin-coated HgSe NCs were heated at a temperature of 150 °C for 15 min to maximize the magnitude of their current, and these films were utilized as the channel layers of TFTs. A representative TFT with a bottom-gate Al₂O₃ layer operated as a depletion-mode one with an n-channel, exhibiting a field effect mobility of 3.9 cm²/Vs and an on/off current ratio of about 10². In addition, the electrical characteristics of the TFT on bent substrates are briefly described.     

Performance of pentacene-based organic field effect transistors using different polymer gate dielectrics

Pentacene-based organic field effect transistors（OFETs） are fabricated using poly（methyl methacrylate）（PMMA） and polyimide（PI） as gate dielectrics,respectively.The fabricated OFETs exhibit reasonable device characteristics.The field-effect mobility,threshold voltage,and on/off current radio are determined to be 3.214 ×10^-2 cm^2 /Vs,-28 V,and 1 ×10^3 respectively for OFETs with PMMA as gate dielectrics,and 7.306×10^-3cm^2 /Vs,-21 V,and 2 ×10^2 for OFETs with PI.Furthermore,the dielectric properties of gate insulator layer are tested and the dipole effect at the semiconductor/dielectrics interface is also analyzed by a model of energy level diagram.     

High-mobility organic thin-film transistors based on a small-molecule semiconductor deposited in vacuum and by solution shearing

The small-molecule organic semiconductor 2,9-di-decyl-dinaphtho-[2,3-b:2′,3′-f]-thieno-[3,2-b]-thiophene (C₁₀-DNTT) was used to fabricate bottom-gate, top-contact thin-film transistors (TFTs) in which the semiconductor layer was prepared either by vacuum deposition or by solution shearing. The maximum effective charge-carrier mobility of TFTs with vacuum-deposited C₁₀-DNTT is 8.5 cm²/V s for a nominal semiconductor thickness of 10 nm and a substrate temperature during the semiconductor deposition of 80 °C. Scanning electron microscopy analysis reveals the growth of small, isolated islands that begin to coalesce into a flat conducting layer when the nominal thickness exceeds 4 nm. The morphology of the vacuum-deposited semiconductor layers is dominated by tall lamellae that are formed during the deposition, except at very high substrate temperatures. Atomic force microscopy and X-ray diffraction measurements indicate that the C₁₀-DNTT molecules stand approximately upright with respect to the substrate surface, both in the flat conducting layer near the surface and within the lamellae. Using the transmission line method on TFTs with channel lengths ranging from 10 to 100 μm, a relatively small contact resistance of 0.33 kΩ cm was determined. TFTs with the C₁₀-DNTT layer prepared by solution shearing exhibit a pronounced anisotropy of the electrical performance: TFTs with the channel oriented parallel to the shearing direction have an average carrier mobility of (2.8 ± 0.3) cm²/V s, while TFTs with the channel oriented perpendicular to the shearing direction have a somewhat smaller average mobility of (1.3 ± 0.1) cm²/V s.