All-optical 40 Gbit/s XOR gate with dual ultrafast nonlinear interferometer

A novel XOR logic gate using dual cascaded ultrafast nonlinear interferometer elements based on semiconductor optical amplifiers is proposed and demonstrated at 40 Gbit/s. The gate is switched at the line rate rather than twice line rate, as in previously reported differential XOR gates.     

Investigation of all-optical error detection circuit using SOA-MZI-based XOR gates at 10 Gbit/s

The operation of an all-optical error detection circuit consisting of an all-optical exclusive OR (XOR) gate for an encoder and two-stage all-optical XOR gates for a decoder using SOA-MZIs has been investigated. 10 and 40 Gbit/s operation of all-optical XOR gates were obtained. Error signals in the syndrome at 10 Gbit/s based on the all-optical XOR gates were achieved for the first time.     

All-optical XOR gate using semiconductor optical amplifiers without additional input beam

The novel design of an all-optical XOR gate by using cross-gain modulation of semiconductor optical amplifiers has been suggested and demonstrated successfully at 10 Gb/s. Boolean AB~ and A~B of the two input signals A and B have been obtained and combined to achieve the all-optical XOR gate. No additional input beam such as a clock signal or continuous wave light is used in this new design, which is required in other all-optical XOR gates.     

Versatile silicon bipolar XOR gate for signal processing up to 8 Gbit/s

A high-speed XOR gate is described, which is well suited for several applications. The circuit was fabricated with a 1.25 mu m double-polysilicon bipolar technology. It operates up to at least 8 Gbit/s, which is by far the highest operating speed reported so far for bipolar XOR gates.<>     

All-optical logic NXOR based on semiconductor optical amplifiers with the effect of amplified spontaneous emission

The performance of all-optical logic NXOR gate based on semiconductor optical amplifiers Mach-Zehnder interferometer(SOAs-MZI)is simulated.The effects of amplified spontaneous emission(ASE)and the input pulse energy on the system’s quality factor are studied.For the parameters used,the all-optical logic gates using SOAs are capable of operating at speed of 80Gbit/s.     

Theoretical investigation of 8 /spl times/ 10-Gb/s WDM signal transmission performance based on gain-equalized SOAs using backward Raman pumping at DCF

We have theoretically investigated 8 /spl times/ 10-Gb/s wavelength-division multiplexing (WDM) signal transmission characteristics based on semiconductor optical amplifiers (SOAs) with equalized gain using discrete Raman amplification (DRA). Gain equalization and low noise figures have been obtained by adjusting the backward Raman pumping power and wavelength at a dispersion compensating fiber (DCF) for each span. Bit-error-rate characteristics were calculated for 8 /spl times/ 10-Gb/s WDM signal transmission over 6 /spl times/ 40-km single-mode fiber (SMF) + DCF links with gain-equalized SOAs using DRAs at DCF. Approximately a 2.5-dB improvement of the receiver sensitivity was achieved by using SOAs and DRAs with optimized Raman pumping. One can easily upgrade the transmission length of a link based on SOAs with an appropriate backward pump laser at each DCF.     

All-optical multiple logic gates with XOR, NOR, OR, and NAND functions using parallel SOA-MZI structures: theory and experiment

The authors have proposed, simulated, and experimentally demonstrated all-optical multiple logic gates using two parallel semiconductor optical amplifier (SOA)-Mach-Zehnder interferometer (MZI) structures that enable simultaneous operations of various logic functions of XOR, NOR, OR, and NAND. The proposed scheme, which is optimized by adjusting the optical gain and phase differences in SOA-MZI structures with creative and systematic method, has great merits to achieve the reshaped output pulses with high extinction ratio and enable the high-speed operation at over 10 Gb/s through performance enhancement of SOAs. Its validity is confirmed through simulation and experiments at 2.5 and 10 Gb/s, respectively.     

Transmission performance of 10-Gb/s 1550-nm transmitters using semiconductor optical amplifiers as booster amplifiers

We have demonstrated the transmission performance of 10-Gb/s transmitters based on LiNbO/sub 3/ modulator using semiconductor optical amplifiers (SOAs) as booster amplifiers. Utilizing the negative chirp converted in SOAs and self-phase modulation induced by high optical power, we can successfully transmit 10-Gb/s optical signals over 80 km through the standard single-mode fiber with the transmitter using SOAs as booster amplifiers. SOAs can be used for booster amplifiers with a careful adjustment of the operating conditions. In order to further understand an SOA's characteristics as a booster amplifier, we model SOAs and other subsystems to verify the experimental results. Based on the good agreement between the experimental and simulation results, we can find the appropriate parameters of input signals for SOAs, such as extinction ratio, rising/falling time, and chirp parameter to maximize output dynamic range and available maximum output power (P/sub o,max/).     

New high-speed bipolar XOR gate with absolutely symmetrical circuit configuration

A new monolithic integrated exclusive OR gate (XOR) in E/sup 2/CL circuit design is presented. The symmetry with respect to both inputs makes it superior to the standard XOR gates in ECL or E/sup 2/CL for several applications. The circuit was realised using a conservative 2 mu m standard silicon bipolar technology.<>     

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of incorporating voltage level conversion into regular CMOS gates by using a second threshold voltage. Proposed level shifter design makes it possible to apply dual supply voltages at gate level granularity with much less overhead compared to traditional level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits designed using 180-nm technology and 17% when 70-nm technology is used.     

All-optical logic NOR gate using two-cascaded semiconductor optical amplifiers

The authors present a novel all-optical logic NOR gate using two-cascaded semiconductor optical. amplifiers (SOAs) in a counterpropagating feedback configuration. This configuration accentuates the gain nonlinearity due to the mutual gain modulation of the two SOAs. The all-optical NOR gate feasibility has been demonstrated delivering an extinction ratio higher than 12 dB over a wide range of wavelength.     

All-optical network subsystems using integrated SOA-based optical gates and flip-flops for label-swapped networks

In this letter, we demonstrate that all-optical network subsystems, offering intelligence in the optical layer, can be constructed by functional integration of integrated all-optical logic gates and flip-flops. In this context, we show 10-Gb/s all-optical 2-bit label address recognition by interconnecting two optical gates that perform xor operation on incoming optical labels. We also demonstrate 40-Gb/s all-optical wavelength-switching through an optically controlled wavelength converter, consisting of an integrated flip-flop prototype device driven by an integrated optical gate. The system-level advantages of these all-optical subsystems combined with their realization with compact integrated devices, suggest that they are strong candidates for future packet/label switched optical networks.     

Modified feedback ECL gate for Gb/s applications

This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference voltage and finds application in digital optical links in which data is typically transmitted single ended. The gate is compared with FECL and ECL gates, and its application to realize logic functions is discussed. A 6-Gb/s series gated decision circuit and a 2-Gbaud/s four-channel optical receiver array employing modified FECL gates are also described     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

40 Gbit/s全光异或门性能仿真

为了提高基于SOA-MZI结构的全光异或门的输出消光比,优化系统性能,将SOA和HNLF相结合,在光通信系统设计软件OptiSystem7.0仿真平台上搭建了基于SOA-MZI的全光异或仿真实验模型,对两路40 Gbit/s的RZ码数据信号进行了全光异或仿真实验。利用HNLF的非线性效应设计了一种优化结构对基于SOA-MZI的全光异或输出信号进行优化,并对优化前后的信号时域波形图和系统眼图进行了比较分析,通过多次反复实验得到一组最佳的系统参数,使得基于SOA-MZI的全光异或门的输出消光比从10 dB提高到约28 dB。实验结果表明:常规的基于SOA-MZI的全光异或门由于相消干涉不彻底造成输出消光比较低,而经过优化,很好地解决了这种问题,提高了异或输出消光比,优化了系统性能。     

A 2Gb/s throughput GaAs digital time switch LSI using LSCFL

A GaAs four-channel digital time switch LSI with a 2.0-Gb/s throughput is developed. This switch consists of 4-bit shift registers, data latches, a counter, a control unit, and I/O buffer gates. The LSI includes 1176 devices (FET's, diodes, and resistors) and its equivalent gate number is 231 gates. Low Power Source Coupled FET Logic (LSCFL) operating in a true/complementary mode is used to ensure high-speed and low-power performance. MESFET's with 0.55-µm gate length are fabricated by the buried p-layer SAINT process, which satisfactorily suppresses short channel effects. Dislocation-free wafers are also used to provide high chip yields of 75 percent. The propagation delay time of the LSCFL basic circuit is 48 ps/gate with 1.4-mW/equivalent gate. The total power dissipation including input and output buffers is 0.64 W. The LSI speed performance is evaluated by measuring toggle frequency of the 1/4 frequency divider. The divider operates typically at 5.1 GHz, maximum 7.5 GHz. The newly developed high-speed digital time switch LSI makes possible time division switching services in TV and high-definition TV transmission systems.     

Reconfigurable All-Optical Logic Gates for Multi-Input Differential Phase-Shift Keying Signals: Design and Experiments

Differential phase-shift keying (DPSK) signals are promising candidate for the long-haul transmission systems. However, the development of the all-optical signal processing techniques for the DPSK signals is still in its infancy, especially the all-optical logic operations. In this work, a general scheme for reconfigurable logic gates for multi-input DPSK signals with integration possibility is proposed. Benefiting from the optical logic minterms developed by two kinds of optical devices, i.e., optical delay interferometers and semiconductor optical amplifiers (SOAs), target logic functions can be realized by combining specific minterms together. The scheme is reconfigured by changing the phase control of the delay interferometers or the input wavelengths. The latter approach was adopted in the experimental trials. Although the outputs of the scheme are on-off keying (OOK) signals, the data format is compatible with all-optical decision circuits where OOK format is preferred. Two- and three-input experiments are carried out at 20 Gbit/s with nonreturn-to-zero DPSK signals. Various logic operations are demonstrated, including full sets of two- and three-input minterms, AND, NOR, XOR, and XNOR logic operations where the AND and NOR logic are derived simultaneously and the XOR and XNOR logic are convertible. The optical SNR as well as the Q-factor of the two- and three-input results are measured and compared. It shows that the input powers to the SOAs are critical in achieving good extinction ratio and the Q-factor of logic results degrades when several minterms are combined. The recovery time of the SOAs need to be optimized as well. Finally, the scaling issues of the scheme are discussed.     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic     

InGaAsP/InP optoelectronic exclusive-OR (XOR) gate operating with optical inputs and outputs

An optoelectronic exclusive-OR (XOR) gate operating with optical inputs and outputs was fabricated. The gate is based on an optoelectronic bistable switch consisting of a light emitting diode (LED) and a heterojunction phototransistor (HPT). The inverter function indispensable for the XOR logic is attained optically by connecting an additional HPT to the bistable switch in parallel. Successful operation of the XOR logic was demonstrated.<>