Method for Designing Efficient Mixed Radix Multipliers

The multiplication of two signed inputs, \(A {\times } B\) , can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ( \(\pm \phi B\) terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the \(\pm \phi B\) terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for \(64\times 64\) bits require \(8.78\) and \(6.55~\%\) less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for \(64\times 64\) bits is almost \(4{\times }\) smaller in comparison with the combinatory solution, although at the cost of about \(5.3{\times }\) slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo \(2^{n}{-}1\) and \(2^{n}{+}1\) multiplier designs for the same width, \(64{\times }64\) bits, provide an Area-Delay-Product similar for the case of the combinatory approach and \(20~\%\) reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.     

Novel Tight Closed-Form Bounds for the Symbol Error Rate of EGC and MRC Diversity Receivers Employing Linear Modulations Over \alpha -\mu Fading

In this paper, we propose novel lower and upper bounds on the average symbol error rate (SER) of the dual-branch maximal-ratio combining and equal-gain combining diversity receivers assuming independent branches. \(M\) -ary pulse amplitude modulation and \(M\) -ary phase shift keying schemes are employed and operation over the \(\alpha -\mu \) fading channel is assumed. The proposed bounds are given in closed form and are very simple to calculate as they are composed of a double finite summation of basic functions that are readily available in the commercial software packages. Furthermore, the proposed bounds are valid for any combination of the parameters \(\alpha \) and \(\mu \) as well as \(M\) . Numerical results presented show that the proposed bounds are very tight when compared to the exact SER obtained via performing the exact integrations numerically making them an attractive much simpler alternative for SER evaluation studies.     

Six Order Cascaded Power Line Notch Filter for ECG Detection Systems with Noise Shaping

This paper presents the design of an operational transconductance amplifier-C (OTA-C) notch filter for a portable Electrocardiogram (ECG) detection system. A six order cascaded filter is utilized to reduce the effect of the power line interference at (50/60 Hz). The proposed filter is based on a programmable balanced OTA circuit. Based on this, PSPICE post layout simulation results for the extracted filter using 0.25  \(\upmu \) m technology and operating under \(\pm \) 0.8 V voltage supply are also given. The six order notch filter provides a notch depth of 65 dB (43 dB for 4th order), input referred noise spectral density with noise shaping of 9  \(\upmu \) Vrms/ \(\surd \) Hz at the pass band frequencies and 9 mVrms/ \(\surd \) Hz at the notch (zero) frequency which provide noise shaping for the ECG signal. These results demonstrate the ability of the filter to be used for ECG signal filtering which is located within 150 Hz.     

A microphone readout interface with 74-dB SNDR

A continuous-time (CT) sigma-delta modulator (SDM) for condenser microphone readout interfaces is presented in this paper. The CT SDM can accommodate a single-ended input and has high input impedance, so that it can be directly driven by a single-ended condenser microphone. A current-sensing boosted OTA-C integrator with capacitive feedforward compensation is employed in the CT SDM to achieve high input impedance and high linearity with low power consumption. Fabricated in a \(0.35\) - \(\upmu\) m complementary metal-oxide-semiconductor (CMOS) process, a circuit prototype of the CT SDM achieves a peak signal-to-noise-and-distortion ratio of 74.2 dB, with 10-kHz bandwidth and \(801\) - \(\upmu\) W power consumption.     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

Downlink SINR Study in Multiuser Large Scale Antenna Systems

In this paper, the downlink signal-to-interference-plus-noise ratio (SINR) performance in multiuser large scale antenna systems with matched filter (MF) and regularized zero-forcing (RZF) precoding is investigated. The probability density function (PDF) for MF is derived and the distribution in high signal-to-noise ratio (SNR) regime is studied. Results indicate that the PDF of downlink SINR for MF converges to \(\mathcal F\) distribution when the interference is dominant over noise. For MF, the asymptotic SINR is just the reciprocal of the ratio of the number of users \(U\) to the number of transmit antennas \(N\) , and is irrelevant to the average transmit power when \(N\) and \(U\) grow with fixed ratio. However, when \(U\) is a large constant, the transmit power could be proportional to \(\ln N \big /N \) to maintain a specified quality of service, as a result of the large scale antenna system effect. In addition, the closed form of asymptotic SINR for RZF is derived by solving two mathematical expectations related to eigenvalues of large dimensional random matrices. Simulation results validate the derived PDF and analytical results.     

Inter-layer correlation considered R-D models and Lagrange multiplier for SVC MGS coding

Traditional rate-distortion (R-D) model-based Lagrange multiplier \(\lambda \) that is employed by H.264/SVC does not consider the inter-layer correlation. This paper presents new R-D models and \(\lambda \) which exploits inter-layer correlation for coding modes that perform residual prediction in H.264/SVC medium-grain quality scalability (MGS) coding. We have observed that in MGS coding, the prediction error of modes performing residual prediction is approximately equal to the reconstruction error of the corresponding macroblock in the reference layer. Based on that observation, we investigate the distribution \(f_r \) of transformed residual prediction error signals and prove that \(f_r \) is related to the quantization step of the corresponding macroblock in the reference layer. In such a case, both the conventional \(\lambda \) and the R-D models in the literature that are derived independently of inter layers are not much fit for residual prediction modes any more. Thus, we build more appropriate R-D models depending on the derived distribution and develop a new \(\lambda \) from the R-D models. Experimental results show that when residual prediction is enabled, the proposed scheme by using the new Lagrange multiplier achieves an average PSNR gain of 0.47 dB and up to more than 1 dB over the scheme using the conventional Lagrange multiplier.     

Anisotropic Thermopower of the Kondo Insulator \hbox {CeRu}_4\hbox {Sn}_6

The intermetallic compound \(\hbox {CeRu}_4\hbox {Sn}_6\) has been tentatively classified as Kondo insulator. This class of material, especially non-cubic representatives, is not yet fully understood. Here we report thermopower measurements on single-crystalline \(\hbox {CeRu}_4\hbox {Sn}_6\) between 2 K and 650 K, along the main crystallographic directions. Large positive thermopower is observed in the directions along which the hybridization is strong and a Kondo insulating gap forms. A negative contribution to the thermopower dominates for the crystallographic \(c\) axis where hybridization is weak and metallicity prevails.     

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low ( \(\sim \) 0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage \(V_\mathrm{L}\) ( \(\sim \) 0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/ \(V_\mathrm{DD})^{ 2 }\,\times \) 100 %) due to reduced voltage swing (from \(V_\mathrm{DD }\)  = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a \(256 \times 64\) bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.     

Construction of (2k,k, 2) Convolutional Codes with Double-Loop Cyclic Codes

In this paper, by taking multiple-time information in blocks into the coding of linear block codes, a new class of (2 \(k\) , \(k\) , 2) convolutional codes is constructed, by which a new way of constructing long codes with short ones is obtained. After that, the type of embedded codes is determined and the optimal values of the linear combination coefficients are derived by using a three-dimensional state transfer matrix to analyze and testify the constructing mechanism of the codes. Finally, the simulation experiment tests the error-correcting performance of the (2 \(k\) , \(k\) , 2) convolutional codes for different value of \(k\) , it is shown that the performance of the new convolutional codes compares favorably with that of traditional (2, 1, \(l\) ) convolutional codes.     

Delay-dependent robust H_\infty control for 2-D discrete nonlinear systems with state delays

This paper investigates the problem of robust \(H_\infty \) control for a class of 2-D (two-dimensional) discrete state delayed systems with sector nonlinearity described by a model of Roesser type. Firstly, a delay-dependent sufficient condition of robust exponential stability for such 2-D discrete systems is derived in linear matrix inequalities (LMIs) form. Secondly, a delay-dependent exponential stability criterion with \(H_\infty \) performance for the considered systems is also proposed. Then a state feedback \(H_\infty \) controller is constructed based on the above results. Finally, numerical examples are given to illustrate the effectiveness of the proposed method.     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

Approximation algorithms for broadcasting in duty cycled wireless sensor networks

Broadcast is a fundamental operation in wireless sensor networks (WSNs). Given a source node with a packet to broadcast, the aim is to propagate the packet to all nodes in a collision free manner whilst incurring minimum latency. This problem, called minimum latency broadcast scheduling (MLBS), has been studied extensively in wireless ad-hoc networks whereby nodes remain on all the time, and has been shown to be NP-hard. However, only a few studies have addressed this problem in the context of duty-cycled WSNs. In these WSNs, nodes do not wake-up simultaneously, and hence, not all neighbors of a transmitting node will receive a broadcast packet at the same time. Unfortunately, the problem remains NP-hard and multiple transmissions may be necessary due to different wake-up times. Henceforth, this paper considers MLBS in duty cycled WSNs and presents two approximation algorithms, BS-1 and BS-2, that produce a maximum latency of at most \((\Delta -1) TH\) and \(13TH\) respectively. Here, \(\Delta\) is the maximum degree of nodes, \(T\) denotes the number of time slots in a scheduling period, and \(H\) is the broadcast latency lower bound obtained from the shortest path algorithm. We evaluated our algorithms under different network configurations and confirmed that the latencies achieved by our algorithms are much lower than existing schemes. In particular, compared to OTAB, the best broadcast scheduling algorithm to date, the broadcast latency and transmission times achieved by BS-1 is at least \(\frac{1}{17}\) and \(\frac{2}{5}\) that of OTAB respectively.     

A 3–10 GHz Ultra Wideband Receiver LNA in 0.13 \mu m CMOS

A fully integrated low-power, low-complexity ultra wideband (UWB) 3–10 GHz receiver front-end in standard 130 nm CMOS technology is proposed for UWB radar sensing applications. The receiver front-end consists of a full UWB band low-noise amplifier and an on-chip diplexer. The on-chip diplexer has a 1 dB insertion loss and provides a \(-\) 30 dB isolation. The diplexer switch was co-designed with the receiver input matching network to optimize the power matching while simultaneously achieving good noise matching performance. The receiver low-noise amplifier provides a 3–10 GHz bandwidth input matching and a power gain of 17 dB. The overall receiver front-end consumes an average power of 13 mW. The core area of the transceiver circuit is 500 \(\mu \) m by 700 \(\mu \) m.     

A Novel 2.5–3.1 GHz Wide-Band Low-Noise Amplifier in 0.18 \upmu \hbox {m} CMOS

Aiming for the simultaneous realization of constant gain, accurate input and output impedance matching and minimum noise figure (NF) over a wide frequency range, the circuit topology and detailed design of wide broadband low noise amplifier (LNA) are presented in this paper. A novel 2.5–3.1 GHz wide-band LNA with unique characteristics has been presented. Its design and layout are done by TSMC 0.18  \(\upmu \hbox {m}\) technology. Common gate stage has been used to improve input matching. In order to enhance output matching and reduce the noise as well, a buffer stage is utilized. Mid-stages which tend to improve the gain and reverse isolation are exploited. The proposed LNA achieves a power gain of 15.9 dB, a NF of 3.5 dB with an input return loss less than \(-\) 11.6, output return loss of \(-\) 19.2 to \(-\) 19 and reverse isolation of \(-\) 38 dB. The LNA consumes 54.6 mW under a supply voltage of 2 V while having some acceptable characteristics.     

Positive L_1 Observer Design for Positive Switched Systems

This paper investigates the problem of \(L_1\) observer design for positive switched systems. Firstly, a new kind of positive \(L_1\) observer is proposed for positive switched linear delay-free systems with observable and unobservable subsystems. Based on the average dwell time approach, a sufficient condition is proposed to ensure the existence of the positive \(L_1\) observer. Under the condition obtained, the estimated error converges to zero exponentially, and the \(L_1\) -gain from the disturbance input to the estimated error is less than a prescribed level. Then the proposed design result is extended to positive switched systems with mixed time-varying delays, where the mixed time-varying delays are presented in the form of discrete delay and distributed delay. Finally, two numerical examples are given to demonstrate the feasibility of the obtained results.     

An Ideal Multi-secret Sharing Scheme Based on Connectivity of Graphs

Secure communication has become more and more important for many modern communication applications. In a secure communication, every pair of users need to have a secure communication channel (each channel is controlled by a server) In this paper, using monotone span programs we devise an ideal linear multi-secret sharing scheme based on connectivity of graphs. In our proposed scheme, we assume that every pair of users, \(p\) and \(q\) , use the secret key \(s_{pq} \) to communicate with each other and every server has a secret share such that a set of servers can recover \(s_{pq} \) if the channels controlled by the servers in this set can connect users, \(p\) and \(q\) . The multi-secret sharing scheme can provide efficiency for key management. We also prove that the proposed scheme satisfies the definition of a perfect multi-secret sharing scheme. Our proposed scheme is desirable for secure and efficient secure communications.     

Minimum payment collaborative sensing network using mobile phones

Mobile phones with embedded sensors have been applied in various collaborative sensing applications. To encourage mobile phone users to perform collaborative sensing, the data demanders usually pay mobile phone users for required data. In this paper, we study the Minimum Payment of Attaining the Required Data with mobile phones (MPARD) problem in collaborative sensing network: given sensing regions \(R = \{R_1, R_2, \ldots , R_m\}\) , the set of requisite data \(D_i\) for each sensing region \(R_i\) and a set of mobile phones \(M\) , the \(MPARD\) problem studies how to select mobile phones to obtain all the required data such that the data demanders’ total payment to mobile phone users is minimized. In reality, some systems need the fresh sensing data from mobile phones at each pre-determined time slot, and others don’t require the real-time data and the sensing data from previous time slots is also deemed useful. Based on the above two different requirements of data timeliness, we first define two subproblems derived from \(MPARD\) problem: \(MPARD_t\) and \(MPARD_p\) . After that, for each subproblem, we propose an approximation algorithm for the situation where the trajectories of mobile phones are determinate and a heuristic for the situation where trajectories are unknown. Simulation results demonstrate that our algorithms are efficient.     

Outage Performance of Hybrid Decode–Amplify–Forward Protocol with the nth Best Relay Selection

In this paper, we consider the Hybrid Decode–Amplify–Forward protocol with the \(n\) th best-relay selection scheme. In the best-relay selection scheme, the best relay only forwards the source signal to the destination, regardless of working in the Amplify-and-Forward mode or the Decode-and-Forward mode. However, the best relay might be unavailable due to some reasons; hence we might bring into play the second, third or generally the \(n\) th best relay. We derive closed-form expression for the outage probability using the probability density function and moment generating function of the signal-to-noise ratio of the relayed signal at the destination node. Results show that with the \(n\) th best relay the diversity order is equal to \((m-n+2)\) where \(m\) is the number of relays. Simulation results are also given to verify the analytical results.     

Design of An Arcak-Type Generalized H_2 Filter for Delayed Static Neural Networks

In this paper, an Arcak-type generalized \(H_2\) filter is designed for a class of static neural networks with time-varying delay. By employing some inequalities and constructing a suitable Lyapunov functional, a delay-dependent condition is derived by means of linear matrix inequalities such that the filtering error system is globally asymptotically stable and a prescribed generalized \(H_2\) performance is achieved. It is shown that the design of such a desired filter for a delayed static neural network is successfully transformed into solving a convex optimization problem subject to some linear matrix inequalities. It is thus facilitated readily by some standard algorithms. A numerical example is finally provided to show the effectiveness of the developed approach. A comparison on the generalized \(H_2\) performance for different gain parameters of the activation function is also given.