GaAs Ultra-High-Speed Prescaler/Phase Frequency Comparator Using LSCFL (Short Paper)

A high-speed, low-power prescaler/phase frequency comparator (PFC) medium scale integration (MSI) circuit for a phase-locked stable oscillator is designed and fabricated using GaAs MESFET low-power source-coupled FET logic (LSCFL) circuitry. The construction of the 1/64 frequency divider prescaler/PFC is designed to obtain high-speed and low-power operation. The fabrication process used is buried p-layer SAINT with a 0.5-µm gate length. The fabricated prescaler/PFC MSI circuit, mounted on a newly developed high-frequency package, operates up to 7.6 GHz with a power dissipation of 730 mW.     

Ultra-High-Speed GaAs Monolithic Prescaler and Phase Frequency Comparator IC

A high-speed, low-power prescaler and phase frequency comparator (PFC) IC for a phase-lock stable oscillator was designed and fabricated on a single chip using GaAs MESFET BFL circuitry. The gate width of the master-slave T-type flip-flops used in designing the 1/32 frequency divider prescaler was determined by circuit simulations. The fabricated 1/32 prescaler operated up to 8.0 GHz while the fabricated monolithic prescaler and PFC IC performed stable division, and phase and frequency comparison at input frequencies up to 4.8 GHz with a chip power dissipation of only 715 mW.     

一种基于新的优化结构和动态电路技术CMOS双模预分频器

提出了一种应用新的电路结构和动态电路技术的双模预分频器,它已用0.25μm CMOS数字工艺实现.新的优化结构减少了电路的传输延迟,提高了电路速度.基于这种优化结构和动态电路技术,提出了改进的D型触发器.为了验证其功能,制作了一个试验型芯片.经测试,该分频器在可以工作于GHz频率范围;在电源电压为2.5V,输入频率为2.5GHz时,其功耗仅为35mW(包括三个功耗很大的输出缓冲器的功耗).由于其具有良好的性能,该分频器可应用于许多射频系统中.     

一种宽分频范围的CMOS可编程分频器设计

设计了一种基于双模预分频的宽范围可编程分频器。对预分频器的逻辑电路进行了改进,提高了最高工作频率,同时,引入输入缓冲级,增加了低频时分频器的输入敏感性。基于Chartered 0.25μm厚栅CMOS工艺,在SpectreRF中仿真,分频器可在50MHz～2.2GHz频率范围正常工作。流片测试结果表明,该分频器可正常工作在作为数字电视调谐芯片本振源的PLL中,对80～900MHz的VCO输出信号,实现256～32767连续分频。     

A Si bipolar 21-GHz/320-mW static frequency divider

A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V_ce=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz)     

A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2)latch and its application in a dual-modulus prescaler

A high speed dual-phase dynamic-pseudo NMOS ((DP)²) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 μm CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 μm CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 μm CMOS process. A 25% reduction of the maximum operating frequency for a ~60% reduction of the power consumption should be a useful tradeoff     

一种基于新的优化结构和动态电路技术CMOS双模预分频器

提出了一种应用新的电路结构和动态电路技术的双模预分频器,它已用0.25μm CMOS数字工艺实现.新的优化结构减少了电路的传输延迟,提高了电路速度.基于这种优化结构和动态电路技术,提出了改进的D型触发器.为了验证其功能,制作了一个试验型芯片.经测试,该分频器在可以工作于GHz频率范围;在电源电压为2.5V,输入频率为2.5GHz时,其功耗仅为35mW(包括三个功耗很大的输出缓冲器的功耗).由于其具有良好的性能,该分频器可应用于许多射频系统中.     

A 23.6 GHz sub-half-micrometer E/D MODFET divide-by-32/64 staticprescaler

An application-ready prescaler with performance competitive with state-of-the-art R&D dividers was designed to be a high-performance replacement for standard ECL parts in instruments. It is fabricated in a proven self-aligned contact sub-half-micrometer GaAs-based enhancement/depletion-mode (E/D-mode) MODFET IC process that utilizes sidewall-spacer self-alignment technology to obtain 0.3-0.5 μm gate length with conventional high-throughput contact lithography. With pseudomorphic InGaAs channels, 30 MHz to 23.6 GHz prescaler operation is demonstrated at room temperature. The performance improves at 0°C, while at 70°C the upper frequency typically drops by 2 GHz. Correct high-speed pulse-mode operation requires (1) presetting which does not degrade the performance and (2) suppression of self-oscillation during quiet periods between pulse bursts. The circuit design provides for both, and pulse-mode operation without ringing, or pulse loss, at 22.4 GHz (present testing limit) has been confirmed     

Speed optimization of edge-triggered CMOS circuits for gigahertzsingle-phase clocks

In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C_oxWL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-μm CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V     

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz     

A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.     

High-speed divide-by-4/5 counter for a dual-modulus prescaler

A new high-speed divide-by-4/5 counter is developed. Based on this divide-by-4/5 counter, a 3 V 2 M ~1.1 GHz dual-modulus divide-by-128/129 prescaler fabricated with 0.6 μm CMOS technology is presented. Its maximum operating frequency of 1.11 GHz with power consumption of 19.2 mW has been measured at a 3 V supply voltage. In addition, for a power supply of 1.5 V, the circuit consumed 2.67 mW at a maximum input frequency of 520 MHz     

1.2V 6GHz 1.19mW 32/33前置分频器的设计

基于4/5双模SCL分频结构设计了一个高速、低压、低功耗的32/33双模前置分频器。该设计基于TSMC90nm1P9M CMOS工艺,利用Mentor Graphics Eldo工具仿真,结果表明该分频器最高工作频率达6GHz,在电源电压1.2V,输入6GHz情况下,功耗仅1.19mW。     

A high-speed multimodulus HBT prescaler for frequency synthesizerapplications

A high-speed variable modulus prescaler that divides the input clock frequency by 128 up to 255 with unit step increment has been implemented with heterojunction bipolar transistor (HBT) technology. A maximum operating frequency of 9.72 GHz with power consumption of 650 mW has been measured. The high-speed performance is attributed to the circuit design, which minimizes the critical path delay, and the intrinsic high-speed characteristics of HBT technology. The phase noise of the prescaler is important for frequency synthesizer applications. With 6.24-GHz input frequency, the phase noise was -110 dBc/Hz at 100-Hz offset frequency and -120 dBc at 1-kHz offset frequency. The noise floor decreases as the input frequency decreases. Phase noises of -125 dBc/Hz at 100-Hz offset and -135 dBc/Hz at 1-kHz offset were obtained for a 1.2-GHz input frequency     

An Ultra-High-Speed GaAs Prescaler Using a Dynamic Frequency Divider

A high-speed, low-power-consumption prescaler for a phase lock stable oscillator is designed and fabricated with a GaAs MESFET BFL circuit. The prescaler of a 1/32 frequency divider is composed of a dynamic frequency divider for the prescaler first stage, a newly developed dual-phase signal generator, and master-slave T-type flip-flops for the presealer post stages. The fabricated 1/32 prescaler operated up to 8.5 GHz at only 540 mW. The 1/2 dynamic frequency divider corresponding to the prescaler first stage shows a maximum operation frequency of 13.2 GHz at only 115 mW.     

A 10-GHz frequency divider using selectively doped heterostructure transistors

We report the first complementary clocked frequency divider using dual gate selectively doped heterostructure transistors (SDHT's). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate, separation in the dual gate SDHT's are 1 µm. A maximum dividing frequency of 10.1 GHz at 77 K was achieved; at this frequency the circuit dissipated 49.9 mW at 1.67-V bias. This is the highest operating frequency reported for static frequency dividers at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97-V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9-mW power dissipation at 1.45-V bias.     

A self-aligned gate III-V heterostructure FET process forultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits

A planar ion-implanted self-aligned gate process for the fabrication of high-speed digital and mixed analog/digital LSI/VLSI integrated circuits is reported. A 4-b analog-to-digital converter, a 2500-gate 8×8 multiplier/accumulator, and a 4500-gate 16×16 complex multiplier have been demonstrated using enhancement-mode n⁺ -(Al,Ga)As/MODFETs, superlattice MODFETs, and doped channel heterostructure field-effect transistors (FETs) whose epitaxial layers were grown by molecular-beam epitaxy. With nominal 1-μm gate-length devices, direct-coupled FET logic ring oscillators with realistic circuit structures have propagation delays of 30 ps/stage at a power dissipation of 1.2 mW/stage. In LSI circuit operation, these gates have delays of 89 ps/gate at a power dissipation of 1.38 mW/gate when loaded with an average fan-out of 2.5 gates and about 1000 μm of high-density interconnects. High-performance voltage comparator circuits operated at sampling rates greater than 2.5 GHz at Nyquist analog input rates and with static hysteresis of less than 1 mV at room temperature. Fully functional 4-b analog-to-digital circuits operating at frequencies up to 2 GHz were obtained     

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-typeflip-flops

A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 μm CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage     

Continuously clocked 1 GHz GaAs CCD

The continuously clocked operation of a buried channel, Schottky-barrier gate GaAs CCD is described at clock frequencies in excess of 1 GHz. A charge transfer efficiency of >0.9999 per transfer is measured at low frequency and 0.994 per transfer at 1 GHz. It is postulated that the high frequency transfer efficiency is a limitation of the equipment.     

Performance of modulation-doped charge-coupled devices (MD-CCD's)in the microwave and millimeter-wave bands

A two-phase, modulation-doped charge coupled device (MD-CCD) has been characterized by both phase shift and charge transfer efficiency (CTE) measurements from 1.25 MHz to 16.4 GHz. Both two-dimensional transient simulations and experimental evidence support the conclusion that the cutoff frequency for transport of discrete charge packets emulates the cutoff frequency of small signal HEMT devices in the short gate length regime. These simulations predict a CTE of almost 0.999 at 40 GHz for an In_0.53Ga_0.47As channel device. The device is fabricated using conventional MMIC processing techniques. In addition, measurement methods used for characterization of a prototype 5-stage delay line chip agree well with simulations using a new CCD SPICE model