一种基于PJFET输入的高压摆率集成运算放大器

基于双极型集成工艺设计并制作了一种高压摆率、低输入偏置电流、低输入失调电流的运算放大器。输入级采用p沟道结型场效应晶体管(PJFET)共源结构,有利于减小输入偏置电流,提高信号接收的灵敏度,实现高输入阻抗、低偏置电流、低输入失调电流和高压摆率。增益级采用常规的共射放大电路结构。输出级采用互补推挽输出结构,提升了驱动负载的能力,并克服交越失真。测试结果表明：在电源电压±15 V、25℃环境温度下,开环电压增益为114.49 dB,正压摆率为12.33 V/μs,负压摆率为-9.76 V/μs,输入偏置电流为42.52 pA,输入失调电流为4.23 pA,输出电压摆幅为-13.56～14.16 V,共模抑制比为105.56 dB,电源抑制比为107.91 dB。     

一种低失调高压大电流集成运算放大器

基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。     

基于偏流补偿的低失调运算放大器的设计

基于双极型工艺,设计了一种具有低输入失调电压、低输入偏置电流的运算放大器。电路结构包含偏置电路、差分输入级电路、中间级电路和输出级电路。差分输入级电路采用共射-共基耦合对,能够降低失调电压,并且采用基极电流补偿结构抵消输入偏置电流在外围电路上所产生的影响,提高电路精度。中间级为整个电路提供增益,并且将双端输入信号转换为单端输出信号。输出级电路为AB类输出级,具有低静态功耗,能够提高电路效率,增大电路带负载能力并为负载提供更多功率。电路采用齐纳修调技术,在封装后对芯片进行修调,避免封装后引入的二次失调。流片后测试结果表明：在±15 V电源电压条件下,输入失调电压≤10μV,输入偏置电流≤3 nA,输入失调电流≤1.5 nA,大信号电压增益≥110 dB。     

微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

一个低噪声轨到轨输入输出范围的运算放大器

设计了一个轨到轨输入输出范围的低噪声运算放大器.在输入级采用电流补偿的方法来稳定该运算放大器在整个输入共模范围内的跨导,在输出级使用AB类的输出方法来提高运算放大器的输出范围,并运用双极晶体管比较低的闪烁噪声来改善该运算放大器的噪声性能,以此提高该运算放大器的动态范围.     

极低输入电压噪声高精度运算放大器

单组装的LMP7731及双组装的LMP7732低电压高精度放大器都具有低噪声、低偏移电压和轨到轨输入／输出（RRIO）的特性。这两款运算放大器均内置双极输入级及输入偏压消除电路，因此输入电流可降低至1．5nA。此外，它们都可在1．8～5．5V的供电电压范围内操作，而且直流电偏移电压只有40μV，增益带宽则高达22MHz，耗电量仅为2mA。     

恒跨导轨对轨CMOS运算放大器的设计

为了提高运算放大器对电源电压的利用率,基于GSMC 0.18 μm CMOS工艺模型,设计了一种高增益恒跨导轨对轨CMOS运算放大器。该运算放大器的输入级采用了互补差分对,并通过3倍电流镜法保证输入级总跨导在整个共模输入范围内恒定;为了获得较大的增益和输出摆幅,中间级采用了折叠式共源共栅结构;输出级采用了AB类输出控制电路,使输出摆幅基本实现了轨对轨。在3.3 V供电电压以及1.6 V输入电压下,该放大器的直流增益为126 dB,单位增益带宽为50 MHz,相位裕度为65°。电路结构简单,易于调试,可大大缩减设计周期和成本。     

一款适用于高速读出电路的输出级运算放大器设计

〖JP+1〗CMOS运算放大器是红外探测器系统读出电路的重要模块,其性能直接影响红外读出电路性能。本文设计了一款适用于高速读出电路的输出级运算放大器,在负载电阻100 kΩ,负载电容25 pF的条件下,使读出电路的工作频率大于20 MHz。输出级运算放大器由折叠共源共栅差分运放和甲乙类推挽反相运放级联构成。折叠共源共栅差分运放可以实现电路高增益、大输出电压范围和高输出阻抗,同时可以有效减小放大器输入端的米勒电容效应。甲乙类推挽反相运放具有高电压电流转换效率,可以灵活地从负载得到电流或者向负载提供电流,实现高电流增益,驱动大负载。两级运放之间通过米勒电容实现频率补偿,保证运放的稳定性。本文设计的高速输出级运算放大器基于SMIC 018μm工艺设计,最终实现指标:功耗不大于10mW,运放增益>84dB,相位裕度79°,单位增益带宽>100 MHz,噪声78 μV(1～500 MHz),输出电压范围1～5 V,建立时间<15ns。通过设计高速输出级运算放大器,红外读出电路的读出速率和帧频得到有效提高。     

一种低失调运算放大器的设计

基于Bipolar工艺设计,结合激光修调技术,实现一种四通道、低失调、低功耗、高增益的运算放大器。电路整体结构包含：基准偏置电路、差分输入及偏置补偿电路、中间级电路、输出及过流保护电路。输入级选择差分输入结构,采用输入偏置补偿设计,降低了输入失调电压和偏置电流;中间级采用射随器结构,结合密勒补偿电容及零点电阻,提高电路的稳定性;输出级采用B类的输出结构,结合过流保护设计,增加电路的安全性。电路封装后测试：输入失调电压10μV,输入偏置电流0.5nA,大信号电压增益130 dB,电源电流2.4mA,增益带宽积1.5MHz,噪声电压7.34nV/√Hz。     

一种具有基极补偿技术的高速运算放大器

介绍了一种基于高速互补双极型工艺设计的宽带高速运算放大器。该运放输入级采用折叠式共射-共基结构能够增大输入级带宽,改进型威尔逊电流镜作为有源负载将差分输入信号转换为单端输出信号,并提高输入级差分增益;通过基极补偿技术补偿输入对管基极电流,降低输入偏置电流,提高运放精度。输出级采用双缓冲AB类输出级,能够消除交越失真,提高运放带负载能力,并为负载提供较大功率。Spectre仿真结果表明：在±15 V,25℃,1 kΩ负载电阻和10 pF负载电容条件下输入偏置电流为34.8 nA,静态电流≤8 mA,单位增益带宽365 MHz,压摆率428.1 V/μs, 0.01%精度建立时间为42.3 ns。     

一种低失调高速宽带通用运算放大器

通过理论分析和流片测试,研究了一种四通道低失调、高速宽带通用运算放大器。输入级采用发射极反馈电阻和展宽频带电容,提高稳定性和转换速率。详细分析了减小输入失调电压和失调电流的补偿电路以及全NPN输出级。电路采用标准双极工艺制造,四通道芯片总面积为3.68 mm×2.29 mm,采用双列直插封装。测试结果为:GBW≥6 MHz、SR≥9 V/μs,全温失调电压小于2 mV(-55℃~+125℃),平均温度系数小于5μV/℃,可以在通用模拟系统中广泛使用。     

一种用于水听器电压检测的模拟前端电路

提出了一种用于水听器电压检测的模拟前端电路,包括低噪声低失调斩波运算放大器,跨导电容(gm-C)低通滤波器,增益放大器三部分主体电路;低噪声低失调斩波运算放大器用于提取水听器前端传感器输出的微弱电压信号;gm-C低通滤波器用于滤除电压信号频率外的高频噪声和高次谐波;最后经过增益放大器放大至后级模数转换器的输入电压范围,输出数字码流;芯片采用台积电(TSMC)0.18μm单层多晶硅六层金属(1P6M)CMOS工艺实现。测试结果表明,在电源电压1.8 V,输入信号25 kHz和200 kHz时钟频率下,斩波运放输入等效失调电压小于110μV;整体电路输出信号动态范围达到80 dB,功耗5.1 mW,满足水听器的检测要求。     

A differential-input,differential-output current mode operational amplifier

A current operational amplifier with differential input and differential output is described. The amplifier is based on the parallel connection of a CCII+ current conveyor and a CCII? current conveyor followed by a differential output transconductance gain stage. The performance of the amplifier is analysed and experimental results obtained from an implementation using standard operational amplifiers and current mirrors realized using transistor arrays are presented and compared to the theoretical analysis. It is concluded that the static small signal open loop gain and the frequency response matches the performance of conventional voltage operational amplifiers. The input offset and bias errors and the common mode rejection are shown to be strongly dependent on the matching accuracy of the current mirrors used in the conveyors. The proposed configuration can easily be integrated into a monolithic amplifier in either CMOS or bipolar technology.     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A wide-band operational amplifier with a new output stage and a simple frequency compensation

Innovations in circuit design have resulted in a high-performance wide band operational amplifier made by standard integrated-circuit production processes. A new class-B output circuit with very low distortion and high quiescent current stability a coupling method for differential amplifier stages incorporating the elimination of amplifier stages at high frequencies to obtain a first-order frequency response and an input stage combined with a level shift with lateral p-n-p transistors having capacitive feed forward to increase the bandwidth are used in this amplifier. A unity gain bandwidth of 50 MHz with an open-loop voltage gain of 3.10/SUP 5/ and an input bias current of 10 nA are obtained.     

一种适用于传感器信号检测的斩波运算放大器

提出一种适合传感器微弱信号检测应用的全差分低噪声、低失调斩波运算放大器。采用两级折叠共源共栅运放结构,基于斩波稳定及动态元件匹配技术,通过在运放低阻节点的电流通路上添加斩波开关的设计方式,增加了运放的输入信号带宽和输出电压摆幅。芯片采用TSMC 0.18μm 1P6MCMOS工艺实现。测试结果表明,在1.8V电源电压,25kHz输入信号和300kHz斩波频率下,斩波运放输入等效失调电压小于120μV,在10Hz～1kHz之间,输入等效噪声为5nV/Hz^1/2,最高开环增益为84dB,单位增益带宽为4MHz。     

一种用于视频信号处理的高速宽带运算放大器

基于高速亚微米互补双极工艺,设计了一种用于视频信号处理的高速宽带运算放大器。电路内部采用高速输入差分对、电流型放大单元、Rail-to-Rail输出单元等结构进行信号传输和放大。对开环增益提升、高速电压-电流信号转换、满摆幅输出设计以及频率稳定性补偿等关键技术进行分析,利用Spectre软件进行仿真。流片后的测试结果表明,在±5 V工作电压下,该放大器的－3 dB带宽≥200 MHz,失调电压≤5 mV,电源电流≤6 mA,满足高速通信、高速ADC前端信号采集、视频信号处理等各种场合的应用需求。