Implementation of an SDR platform using GPU and its application to a 2?��?2 MIMO WiMAX system

Conventional communication systems have been implemented using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs), especially for software defined radio (SDR) functionality. We propose a scheme that uses a graphics processing unit (GPU) in place of the conventional DSPs or FPGAs for the implementation of an SDR-based communication system. The GPU, a high-speed parallel processor with multiple arithmetic logic units, is adopted for the signal processing of the physical layer required for the parallel processing in an SDR system. The compute unified device architecture (CUDA) based on the C language provides a software development kit (SDK) for the modem application of the GPU. Therefore we utilize the CUDA SDK to implement the real-time modem function. This paper presents an implementation of a 2 × 2 multiple-input multiple-output (MIMO) WiMAX system employing a GPU as the real-time modem. By installing a radio frequency module on top of the GPU modem, we implement a real-time transmission system for video data. The performance of the proposed GPU-based system is demonstrated by comparing its operation time against that of the conventional DSP-based system.     

Implementation of smart antenna API and transceiver API in software communication architecture for a wireless innovation forum standard

This study presents an implementation of the standard smart antenna (SA) application programming interface (API) and Transceiver API developed by the wireless innovation forum??s (WINNF) smart antenna working group (SAWG). The API is implemented using the open-source SCA implementation-embedded (OSSIE) developed at Virginia Tech. Our implementation verified that the SA API can be utilized in software communication architecture (SCA)-based software defined radio (SDR) systems. We also verified that the Transceiver API can be realized with a real radio frequency (RF) transceiver module such as universal software radio peripheral2 (USRP2). The SA API enables various functions of multi-antenna systems such as beamforming and multiple input multiple output (MIMO) of spatial multiplexing. These are core technologies prevalent in 4G mobile communication systems. In order to support multi-antenna structures, the Transceiver API has first been extended for multichannel use. The paper details how the API is extended using OSSIE and the current status of the API as a standard within the Wireless Innovation Forum.     

Implementation of an SDR system using an MPI-based GPU cluster for WiMAX and LTE

This paper presents an implementation of a 2?×?2 Multi-Input Multi-Output Software Defined Radio (SDR) Base Station system using a Message Passing Interface (MPI)-based Graphic Processing Unit (GPU) cluster as its modem processor for a high-speed data processing. Recently, GPUs have been widely researched especially for SDR systems because of their capability for exploiting parallel processing using a large number of Arithmetic Logic Units. MPI-based GPU clusters have been adopted in order to further increase performance capability. From our experimental results, it has been found that the implemented system consisting of three GPU nodes can enhance the modem speed by more than 2.5 times compared to a single GPU system. A dual-mode Mobile Device (MD) prototype supporting Worldwide Interoperability for Microwave Access and Long Term Evolution communications systems is implemented. In our design, one of the two waveforms can automatically be selected by the MD itself using a dual-mode controller that determines the reconfiguration of the MD modem depending on the received signal quality.     

一种基于SCA的DSP软件无线电框架实现

在通信行业采甩SDR已是大势所趋,无论是民用还是军用领域都广泛采用这一概念。但是还没有一个框架能将DSP纳入到SDR系统中。为了提高SDR系统的性能,同时保证波形软件的可移植性和通用性,基于软件通信体系结构在DSP上设计实现了软件无线电框架。规范了在软件无线电产品中使用DSP的方法,提高了DSP波形组件的模块化程度及在不同平台上的可移植性和可重用性,使基于SCA的SDR的性能得以提高。     

A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse.     

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm² chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port     

Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform

Software-defined radio (SDR) is a new technology transitioning from research into commercial markets. SDR moves hardware-dominant baseband processing of multiple wireless communication protocols into software on a single chip. New cellular standards, such as HSPA+, LTE, and LTE+, require speeds in excess of 40 Mbps. SNOW 3G is a new stream cipher approved for use in these cellular protocols. Running SNOW 3G in software on our SDR platform provides a throughput of 19.1 Mbps per thread for confidentiality and 18.3 Mbps per thread for integrity. To have secure cellular communications in SDR platforms for these new protocols, the performance of security algorithms must be improved. This paper presents instruction set architecture (ISA) extensions and hardware designs for cellular confidentiality and integrity algorithms using SNOW 3G. Our ISA extensions and hardware designs are evaluated for the Sandbridge Sandblaster^? 3011 (SB3011) SDR platform. With our new SNOW 3G instructions, the performance of confidentiality and integrity improve by 70 and 2%, respectively. For confidentiality, power consumption increased by 2%, while energy decreased by 40%. For integrity, power consumption remained consistent, while energy decreased by 2%.     

A PC-based software receiver using a novel front-end technology

Since the software radio concept was introduced, much progress has been made in the past few years in making it a reality. Many software radio based systems have been designed through the development efforts of both commercial and noncommercial organizations. While the term software radio has meant many things, the ultimate goal in software radio has been the realization of an agile radio that can transmit and receive signals at any carrier frequency using any protocol, all of which can be reprogrammed virtually instantaneously. Such a system places great demands on the limits of data converter and processor technologies since it requires real-time disposition of gigasamples of data produced by direct conversion of wireless signals into digital data. From a processing standpoint, the challenge in software radio is to exploit the three basic processor types-fixed architecture processors, FPGAs, and programmable DSPs/RISCs/CISCs-in such a way as to optimize the three-way trade-offs between speed, power dissipation, and programmability. With respect to the latter characteristic, the issues of high-level language interfaces, portability, and reprogramming speed must be considered. This article describes the architecture and operation of a PC-based software radio receiver. The development environment is a real-time PC-based platform that allows testing to be done in a simple manner using the main software functionality of a PC. The front-end of the receiver implemented in hardware represents a novel wideband design (bandwidth of up to 100 MHz centered at a carrier frequency of up to 2 GHz) that functionally converts wireless signals directly into a gigasample digital data stream in the receiver (and vice versa in the transmitter). This direct conversion approach shows the greatest promise in realizing the main goal of software radio     

Programmable processor implementations of -best list sphere detector for MIMO receiver

An increasing number of standards in wireless communications have encouraged to study programmable processors as platforms for flexible receivers. A multiple-input multiple-output (MIMO) antenna system combined with orthogonal frequency division multiplexing (OFDM) technique has been introduced in many wireless communications standards, such as in the third generation long term evolution (3G LTE). The MIMO-OFDM system requires an efficient detector and a platform support for parallel processing of multiple subcarriers. A K-best list sphere detector (LSD) provides for near optimal decoding performance and a fixed throughput making it an interesting algorithm from the point of view of practical implementations.In this paper, we compare the implementations of the K-best LSD on four processor platforms: a digital signal processor (DSP), software defined radio (SDR), application-specific processor (ASP) and application-specific instruction-set processor (ASIP). The DSP is a popular very long instruction word (VLIW) device (TMS320C6455), the SDR processor employs multithreading and multiple cores (SB3500 core processor), the ASP is based on transport triggered architecture (TTA), while the ASIP is the SDR processor enhanced with a special instruction-set extension for sorting.A 2×2 MIMO antenna system with 64-quadrature amplitude modulation (64-QAM) is assumed. The chosen list sizes K=8 and 16 are based on simulation results carried out in MATLAB environment with the third generation long term evolution (3G LTE) parameters. The proposed ASIP achieved a promising throughput of 32.0 Mbps, where the software defined radio (SDR) implementation on the SB3500 core processor suffers from an inefficient software sorter. The ASP, in which the minimized hardware complexity has been the goal, achieves a throughput of 7.6 Mbps. However, more essential examination is related to the symbol time, which sets strict parallel processing requirements to the programmable processors.     

Signal processing challenges for applying software radio principles in future wireless terminals: an overview

The general idea of software radio is to develop highly integrated radio transceiver structures with high degree of flexibility and multimode capabilities, achieved through increased role of digital signal processing software in defining the functionalities which have traditionally been implemented with analog RF techniques. This paper explores the software radio concept from the receiver architecture and signal processing points of view, with mainly the wireless terminal application in mind. We first discuss the critical issues in alternative receiver architectures with simplified analog parts and increased configurability. We also introduce certain advanced digital signal processing techniques which could potentially relieve some of the essential problems and pave the way towards DSP‐based, highly integrated, and highly configurable terminals. Big emphasis is on efficient digital multirate signal processing methods and complex (I/Q) signal processing. Copyright © 2002 John Wiley & Sons, Ltd.     

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Software-defined radio (SDR) is a revolution in radio design due to the ability to create radios that can self-adapt on the fly. In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software. By simply downloading a new program, a SDR device is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, massively parallel signal processing at higher frequencies are needed to implement a realistic SDR. Thus, FPGAs have been used extensively for implementing essential functions in SDR architectures at lower frequencies. In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The circuit is designed in VHDL, then synthesized and simulated using LeonardoSpectrum Level 3 and ModelSim SE 6, respectively. It operates at a frequency up to 150 MHz and occupies the area of roughly 15 K logic gates.     

Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS

This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRP™) and how it controls calibration and compensation for process, temperature and voltage variations of the analog and RF circuits to meet the required RF performance. A few calibration examples to reduce a DCO bias current and improve device reliability, as well as to optimize transmit modulation and receive performance, are given. The presented circuits and techniques have enabled successful implementation of a commercial single-chip GSM radio in 90 nm CMOS.      

Low‐Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 μm CMOS Technology

This paper presents the experimental results of a low‐power low‐cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 μm CMOS process and occupies 10 mm² of silicon area.     

FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.     

Smart antennas in software radio base stations

The application of adaptive antenna techniques to fixed-architecture base stations has been shown to offer wide-ranging benefits, including interference rejection capabilities or increased coverage and spectral efficiency. Unfortunately, the actual implementation of these techniques to mobile communication scenarios has traditionally been set back by two fundamental reasons. On one hand, the lack of flexibility of current transceiver architectures does not allow for the introduction of advanced add-on functionalities. On the other hand, the often oversimplified models for the spatiotemporal characteristics of the radio communications channel generally give rise to performance predictions that are, in practice, too optimistic. The advent of software radio architectures represents a big step toward the introduction of advanced receive/transmit capabilities. Thanks to their inherent flexibility and robustness, software radio architectures are the appropriate enabling technology for the implementation of array processing techniques. Moreover, given the exponential progression of communication standards in coexistence and their constant evolution, software reconfigurability will probably soon become the only cost-efficient alternative for the transceiver upgrade. This article analyzes the requirements for the introduction of software radio techniques and array processing architectures in multistandard scenarios. It basically summarizes the conclusions and results obtained within the ACTS project SUNBEAM, proposing algorithms and analyzing the feasibility of implementation of innovative and software-reconfigurable array processing architectures in multistandard settings     

Real-time implementation of a reconfigurable IMT-2000 base stationchannel modem

Research suggests that joint methods combining smart antennas, RAKE reception, multi-user detection or other adaptive methods may be practically implemented for IMT-2000 channel modems using computationally simplified algorithms. Using software-defined radio methods, these modems can be employed in a new generation of adaptive multimode base stations which permit software reconfiguration from second- to third-generation air interfaces. Practical implementation is made possible by corresponding advances in hardware technology, including new processors and high-bandwidth I/O fabrics which replace traditional computer buses with their inherent limitations in bandwidth and scalability. In this article adaptive processing research is reviewed, implementation requirements for second- and third-generation base stations are considered, and the capabilities of selected new monolithic silicon devices are examined. A possible implementation approach for a reconfigurable multimode base station channel modem using software defined radio (SDR) design methods is proposed     

RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

SINR estimation and orthogonality factor calculation of DS‐CDMA signals in MIMO channels employing linear transceiver filters

A discrete‐time model of DS‐CDMA signaling using multiple transmit and receive antennas employing linear transceiver filters is derived. For each link, connecting a base‐station to a wireless mobile user, the downlink signal to interference plus noise ratio (SINR) after despreading is derived analytically, and as a by‐product an exact closed‐form solution of the orthogonality factor is obtained. The orthogonality factor is derived for any linear receiver structure that is implemented by a bank of correlators and for any linear combining techniques (such as MRC and MMSE), and for any number of transmit and/or receive antennas that utilize transmit (pre‐RAKE) and receive (post‐RAKE) filtering. The MIMO DS‐CDMA model is derived using a filter representation, and is extended to a vector/matrix formulation that permits a systematic and efficient way of computing the SINR in a radio network simulator. Copyright © 2006 John Wiley & Sons, Ltd.     

Adaptability and Configurability in Cognitive Radio Design on Small Form Factor Software Radio Platform

The recent advances in cognitive radio technology based on software defined radio platforms have extended the capabilities of wireless communication systems. The unique ability of cognitive radios to alter their communication protocols to meet changing system demands make them great candidates for wireless applications that are difficult to implement using conventional wireless terminals. Small form factor platforms make cognitive radio portable and easy to deploy. This paper discusses the design and implementation methodology to build a cognitive radio on small form factor platform with heterogeneous processing architecture. The result of this discussion is a configurable wireless transceiver that features two important concepts of cognitive radio, namely configurability and adaptability.