Software defi ned radio: Part 22 in a series of tutorials on instrumentation and measurement

A software defined radio (SDR) [1] is a communication system that performs many of its required signal processing tasks in a programmable digital signal processing (DSP) engine. The engine is coupled to the air interface of analog circuits and antennae by analog-to-digital and digital-to-analog converters (ADCs and DACs). The SDR's software reprograms the DSP segment of the radio's physical layer to reconFigure the radio system parameters and can thus synthesize multiple radios. The software can also select and alter the air interface components as well as the higher level data processing layers of the radio system.     

Implementation of an SDR platform using GPU and its application to a 2?��?2 MIMO WiMAX system

Conventional communication systems have been implemented using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs), especially for software defined radio (SDR) functionality. We propose a scheme that uses a graphics processing unit (GPU) in place of the conventional DSPs or FPGAs for the implementation of an SDR-based communication system. The GPU, a high-speed parallel processor with multiple arithmetic logic units, is adopted for the signal processing of the physical layer required for the parallel processing in an SDR system. The compute unified device architecture (CUDA) based on the C language provides a software development kit (SDK) for the modem application of the GPU. Therefore we utilize the CUDA SDK to implement the real-time modem function. This paper presents an implementation of a 2 × 2 multiple-input multiple-output (MIMO) WiMAX system employing a GPU as the real-time modem. By installing a radio frequency module on top of the GPU modem, we implement a real-time transmission system for video data. The performance of the proposed GPU-based system is demonstrated by comparing its operation time against that of the conventional DSP-based system.     

基于FPGA的DDC设计及仿真

在软件无线电数字接收机中,从AD前端采集过来的数字信号频率高达72 MHz,如此高的频率使得后端DSP不能直接完成相关的数字信号处理任务。因此合理的设计基于FPGA的DDC,以降低数字信号频率,方便后端DSP实时完成相关的数字信号处理任务就显得尤为重要。在很多数字信号处理系统中,数字信号频率是非常高的,而后端数字信号处理器件几乎不能满足系统的实时性要求,此时通过合理的设计DDC就可以解决上述问题。     

基于DSP FPGA GPP-CPU的软件无线电信号处理平台的硬件设计

DSP FPGA构成的数字硬件系统以其强通用性、灵活性、高处理速度而使其在诸多领域有广泛的应用;GPP(General Purpose Processor)功能强大,不仅可以做复杂的控制算法,还具有强大的数字信号处理能力。本文介绍了一种基于DSP FPGA GPP-CPU的软件无线电信号处理通用硬件平台的设计。     

Antenna design strategy and demonstration for software-defined radio (SDR)

Antennas are a key enabling technology for software-defined radio (SDR). Although software is extremely flexible, SDR??s potential is limited by antenna size and performance. In this paper, we review typical antenna miniaturization techniques and fundamental theories that limit antenna size and performance including operational bandwidth, gain (or range), and radiation pattern. Possible antenna design strategies are discussed to meet the desired specifications in SDR based on observations from the limit theories. The application of strategies to enable multiband (resonant), continuous multiband (frequency independent), and instantaneous, ultra-wideband antennas are discussed qualitatively. Advantages, disadvantages, and design trade-off strategies for different types of antennas are compared from a system-level perspective. A design example for a compact ultra-wideband (UWB) antenna is presented for a software-defined platform. The example involves a direct-conversion radio developed in Wireless@VT that uses a Motorola RFIC having a 100 MHz?C6 GHz operational frequency range with a 9 kHz?C20 MHz channel bandwidth. The example antenna covers frequencies from 450 MHz to 6 GHz instantaneously with approximately 5-dBi realized gain over a finite-size ground plane, including return loss and omni-directional coverage.     

Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform

Software-defined radio (SDR) is a new technology transitioning from research into commercial markets. SDR moves hardware-dominant baseband processing of multiple wireless communication protocols into software on a single chip. New cellular standards, such as HSPA+, LTE, and LTE+, require speeds in excess of 40 Mbps. SNOW 3G is a new stream cipher approved for use in these cellular protocols. Running SNOW 3G in software on our SDR platform provides a throughput of 19.1 Mbps per thread for confidentiality and 18.3 Mbps per thread for integrity. To have secure cellular communications in SDR platforms for these new protocols, the performance of security algorithms must be improved. This paper presents instruction set architecture (ISA) extensions and hardware designs for cellular confidentiality and integrity algorithms using SNOW 3G. Our ISA extensions and hardware designs are evaluated for the Sandbridge Sandblaster^? 3011 (SB3011) SDR platform. With our new SNOW 3G instructions, the performance of confidentiality and integrity improve by 70 and 2%, respectively. For confidentiality, power consumption increased by 2%, while energy decreased by 40%. For integrity, power consumption remained consistent, while energy decreased by 2%.     

基于单通道DRFM的基带干扰源设计

通过对单通道数字射频存储器的原理和结构分析,总结了单通道数字射频存储器的优缺点,并基于单通道数字射频存储结构,引入DSP模块设计了一种基带干扰源,实现了对宽带信号的处理。     

Implementation of LTE system on an SDR platform using CUDA and UHD

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.     

RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

一种基于SCA的DSP软件无线电框架实现

在通信行业采甩SDR已是大势所趋,无论是民用还是军用领域都广泛采用这一概念。但是还没有一个框架能将DSP纳入到SDR系统中。为了提高SDR系统的性能,同时保证波形软件的可移植性和通用性,基于软件通信体系结构在DSP上设计实现了软件无线电框架。规范了在软件无线电产品中使用DSP的方法,提高了DSP波形组件的模块化程度及在不同平台上的可移植性和可重用性,使基于SCA的SDR的性能得以提高。     

Signal processing challenges for applying software radio principles in future wireless terminals: an overview

The general idea of software radio is to develop highly integrated radio transceiver structures with high degree of flexibility and multimode capabilities, achieved through increased role of digital signal processing software in defining the functionalities which have traditionally been implemented with analog RF techniques. This paper explores the software radio concept from the receiver architecture and signal processing points of view, with mainly the wireless terminal application in mind. We first discuss the critical issues in alternative receiver architectures with simplified analog parts and increased configurability. We also introduce certain advanced digital signal processing techniques which could potentially relieve some of the essential problems and pave the way towards DSP‐based, highly integrated, and highly configurable terminals. Big emphasis is on efficient digital multirate signal processing methods and complex (I/Q) signal processing. Copyright © 2002 John Wiley & Sons, Ltd.     

Increasing SDR Receiver Dynamic Range by ADC Diversity

Nowadays, most radio implementations are based on software-defined radio (SDR) technologies. The capabilities of digital signal processing enable new applications like low power wide area networks (LPWAN), which are expected to play a decisive role in the upcoming Internet of Things. Centralized gateways, usually realized in an SDR architecture, are used to connect many thousands of objects to the internet. Due to the high variance of the received signal level, a high dynamic range is required for the SDR receiver front-end. In current receiver architectures, the dynamic range is mainly limited by the analog-to-digital converter (ADC). Several techniques have been proposed to extend the dynamic range by stacking multiple ADCs and driving them with different gain factors. Correlation of quantization noise was identified as key parameter to determine the dynamic range enhancement. This paper compares the proposed techniques and extends existing analysis tools for the use of arbitrary gain factors. Additionally, the influence of further noise sources like thermal noise and jitter are taken into account. The theoretical considerations are supported by simulations and measurements using a real LPWAN SDR implementation.     

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.     

软件无线电信道处理的DSP实现

本文重点研究了软件无线电(Software Defined Radio,SDR)中不同信道的处理技术,其技术关键在于构建不同频段的数字滤波器进行不同信道信息的接收处理.在建立软件无线电信道模型的基础上,利用MATLAB实现了多阶FIR滤波器的设计,并将算法移植到DSP软件设计当中,在DSP的集成开发环境CCS下对FIR滤波进行了仿真,仿真结果达到了SDR的信道处理要求.     

基于软件无线电的伪卫星接收机的设计与实现

提出了基于软件无线电的伪卫星接收机的数学模型和数字平台实现的两种方案：DDC＋DSP方案和FPGA＋DSP方案。通过对这两种方案的比较，得出在伪卫星接收机数字平台的设计中应采用FPGA＋DSP方案。     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

Programmable processor implementations of -best list sphere detector for MIMO receiver

An increasing number of standards in wireless communications have encouraged to study programmable processors as platforms for flexible receivers. A multiple-input multiple-output (MIMO) antenna system combined with orthogonal frequency division multiplexing (OFDM) technique has been introduced in many wireless communications standards, such as in the third generation long term evolution (3G LTE). The MIMO-OFDM system requires an efficient detector and a platform support for parallel processing of multiple subcarriers. A K-best list sphere detector (LSD) provides for near optimal decoding performance and a fixed throughput making it an interesting algorithm from the point of view of practical implementations.In this paper, we compare the implementations of the K-best LSD on four processor platforms: a digital signal processor (DSP), software defined radio (SDR), application-specific processor (ASP) and application-specific instruction-set processor (ASIP). The DSP is a popular very long instruction word (VLIW) device (TMS320C6455), the SDR processor employs multithreading and multiple cores (SB3500 core processor), the ASP is based on transport triggered architecture (TTA), while the ASIP is the SDR processor enhanced with a special instruction-set extension for sorting.A 2×2 MIMO antenna system with 64-quadrature amplitude modulation (64-QAM) is assumed. The chosen list sizes K=8 and 16 are based on simulation results carried out in MATLAB environment with the third generation long term evolution (3G LTE) parameters. The proposed ASIP achieved a promising throughput of 32.0 Mbps, where the software defined radio (SDR) implementation on the SB3500 core processor suffers from an inefficient software sorter. The ASP, in which the minimized hardware complexity has been the goal, achieves a throughput of 7.6 Mbps. However, more essential examination is related to the symbol time, which sets strict parallel processing requirements to the programmable processors.     

双模对讲机中数字编码静噪系统的实现

由于数字对讲机的频谱利用率比模拟对讲机高得多,还由于数字对讲机能够提供模拟对讲机无法达到的数据处理种类及灵活性,因此模拟对讲机的数字化改造进程已势不可挡.在这个过渡时期,需要开发数模兼容的双模对讲机,以满足市场需要并实现平缓过渡.双模对讲机的数字基带信号处理系统已经用数字信号处理器(DSP)实现,以往使用专用芯片实现的...     

数字信号处理技术在软件无线电中的应用

初步探讨了宽带Ａ／Ｄ变换，数字中频处理和ＤＳＰ等现代数字信号处理技术在软件无线电中的应用，根据器件的技术水平给出了具体的实现框图。     

一种低功耗软件无线电信号处理平台

介绍一种应用于软件无线电的数字信号处理平台,通过对平台设计架构、硬件实现方案及软件可配置功能的阐述,提出了GMSK和CPM两种无线通信波形软件实现方案。该平台采用OMAP+FPGA的架构,具有通用性好、扩展性强等特点,适合于高性能、低功耗的应用场合,可广泛应用于在无线通信、导航定位、图像处理等数字信号处理领域。