基于制造成品率模型的集成电路早期可靠性估计

缺陷是影响集成电路成品率与可靠性的主要因素.本文在区分缺陷与故障两个概念的基础上,将缺陷区分为成品率缺陷(硬故障)、可靠性缺陷(软故障)和良性缺陷.利用关键区域的面积,给出了一个缺陷成为"硬故障"或"软故障"的概率,给出了精度较高的IC成品率预测模型.利用成品率缺陷与可靠性缺陷之间的关系,给出了工艺线生产的产品的失效率与该工艺线制造成品率之间的定量关系.在工艺线稳定的条件下,通过该工艺线的制造成品率可以利用该关系式可以有效的估计出产品的失效率,可以有效地缩短了新产品的研发周期.     

A relation model of gate oxide yield and reliability

The relationship between yield and reliability is obviously important for predicting and improving reliability during the early production stage, especially for new technologies. Previous research developed models to relate yield and reliability when reliability is defined as the probability of a device having no reliability defects. This definition of reliability is not a function of mission time and thus is not consistent with reliability estimated from the time-to-first-failure data which is commonly used. In this paper, we present a simple model to tie oxide yield to time-dependent reliability by combining the oxide time to breakdown model with a defect size distribution. We show that existing models become special cases when a single mission time is considered. As the proposed reliability function has a decreasing failure rate, the result is useful for a manufacturer seeking to find an optimal burn-in policy for burn-in temperature, burn-in voltage, and burn-in time.     

On the Relationship of Semiconductor Yield and Reliability

Traditionally, semiconductor reliability has been estimated from the life tests or accelerated stress tests at the completion of manufacturing processes. Recent research, however, has been directed to reliability estimation during the early production stage through a relation model of yield and reliability. Because the relation model depends on the assumed density distribution of manufacturing defects, we investigate the effect of the defect density distributions on the predicted reliability, for a single-area device without repair and for a two-area device with repair, respectively. We show that for any device, reliability functions preserve an ordering of yield functions. It is also pointed out that the repair capability improves only yield but not reliability, resulting in a large value of the factor that scales from yield to reliability. In order to achieve a reliable device, therefore, we suggest to improve yield and to perform the device test such as burn-in if the scaling factor is large.     

基于缺陷均匀分布的集成电路制造成品率与可靠性之间的关系模型

在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.     

Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability ERA

Clear relations have been established between E-sort yield and burn-in, EFR and field failure rates for nearly 50 million high volume products in bipolar, CMOS and BICMOS technologies from different waferfabs. The correlations obey a simple model that assumes that the reliability defect density is a fraction of the waferfab defect density and that rootcauses of failures are the same. The model allows a die size independent prediction and assessment of FIT and PPM reliability levels of an IC just based on its yield, eliminating the need for excessive lifetesting. ‘Maverick’ batches are identified by more than 2 to 3 rejects per batch and can not be eliminated by scrap of low yielding wafers alone. For non-mature technologies only correlations with functional yield are found, the parametric yield loss can be disregarded. Using the results, it is shown how reliability can be improved in a fast and controlled way, even in the 1 digit FIT and PPM reliability era, by reducing waferfab defect density, elimination of special causes and implementation of screens at product test like voltage screen and Iddq testing. As the effect of yield on PPM reject level is not that strong, the latter approach can be very effective in improving reliability.     

Estimating Reliability Growth

Test programs are conducted to identify system failure modes and to estimate reliability. If the system can be changed so that some of the identified failure modes are eliminated and new failure modes are not introduced, the reliability of the system is improved. This paper examines small-sample techniques for estimating the change in reliability without the benefit of test data from the improved system. A decision to make the improvements can be based on the estimated increase in reliability. The procedures used for estimating changes can also be adapted to estimating reliability using data from a test program conducted in stages. For this case, a sample is taken at each stage and changes are made so that all newly identified failure modes which are correctable are eliminated from the system. Simulation is used to study reliability estimators both when just one sample is taken and when sampling is conducted in stages.     

缺陷引起的可靠性和成品率关系研究

为了在满足最低可靠性要求的同时尽量提升Ic的成品率,基于缺陷的泊松分布模型及负二项分布模型研究了由缺陷引起的Ic可靠性和成品率这两者之间的关系,并分别建立了相应的成品率一早期可靠性关系模型。基于成品率一可靠性模型,针对氧化层缺陷模型,采用模拟运算的方法,得到了随时间变化的成品率一可靠性关系模型。模型表明,在满足最低可靠性要求的同时,合理设计老化实验参数,可以最大限度地提高成品率,降低Ic制造成本。最后根据这一模型对Ic老化筛选实验的参数选择提出了优化的建议。     

Real-time furnace modeling and diagnostics

Precise control of process temperature has become increasingly important in today's semiconductor industry. Multizone batch furnaces are used widely in current manufacturing lines, and high reliability of furnace systems is a crucial factor in achieving high product yield. However, uncertainty caused by sensor noise and failure may degrade reliability. In this work, the authors develop a methodology based on thermal modeling and sensor fusion techniques to detect temperature sensor failures, power supply failures, and system faults for the multizone furnace systems. The typical types of failures have been defined. The impact of single failures and different combinations of failures on the system behavior has been studied. The furnace system has been modeled based on both physical considerations and experimental data extraction. The fault detection methodology has been tested in simulations. Principal component analysis is utilized for choosing data types for different fault detection purposes. Sensor fusion is used to enhance reliability. Simulation results show that all different types of failures can be detected when data are rich enough. Experimental results show that all single failures and some of the failure combinations can be estimated when only steady-state and cooling-down data are utilized.     

Bayesian Confidence Limits for the Reliability of Cascade Exponential Subsystems

The problem treated here is that of deriving exact Bayesian confidence intervals for the reliability of a cascade system consisting of N independent subsystems each having an exponential distribution of life with a failure rate which is estimated from life test data. The posterior probability density function of the system reliability is derived in closed form, using the method of the Mellin integral transform. The posterior distribution function is obtained, yielding Bayesian confidence limits on the total system reliability. These results, which are believed to be new for N > 3, have an immediate application to problems of reliability evaluation and test planning.     

An overview of manufacturing yield and reliability modeling forsemiconductor products

This paper presents an overview of yield, reliability, burn-in, cost factors, and fault coverage as practiced in the semiconductor manufacturing industry. Reliability and yield modeling can be used as a foundation for developing effective stress burn-in, which in turn can warranty high-quality semiconductor products. Yield models are described and their advantages and disadvantages are discussed. Both yield reliability relationships and relation models between yield and reliability are thoroughly analyzed in regard to their importance to semiconductor products     

基于IC互连线开路故障的Y/R模型

在半导体制造业中,IC的成品率和可靠性(Y/R)是倍受关注的两个问题.研究表明它们之间存在着显著的相关性.为了表征这种相关性,本文从缺陷造成互连线开路的机理出发,分析了成品率关键面积和可靠性关键面积,提出了IC成品率与可靠性关系模型.通过模拟实验给出了该模型的有效性验证.     

Estimation of system reliability for uncooled optical transmittersusing system reliability function

This paper investigates the system reliability for 155 Mb/s optical transmitters by deriving a system reliability function from reliability data of each component for transmitters, laser diode, photodiode, optical assembly, and driver IC. The reliability data for each component reliability function have been obtained from accelerated aging test. The reliability parameters such as failure rate, mean time-to-failure (MTTF), standard deviation are obtained from a probability plotting method. From the system reliability function, the MTTF of the optical transmitter at 65°C was estimated to be 47000 h with 95% confidence. In this estimation, we introduced modified lifetime of laser diodes and reliability function of optical assembly     

A probabilistic design optimization for MEMS tunable capacitors

This paper presents a design optimization method for MEMS parallel-plate capacitors under fabrication uncertainties. The objective of the optimization problem is to maximize the production yield considering the fabrication tolerances. The method utilizes aspects of the advanced first-order second-moment (AFOSM) reliability method in probabilistic design to find a linearized feasible region for performance functions and uses an analytical double-bounded-probability distribution function (DB-PDF) to approximate the distribution of random variables. Then, it attempts to place the tolerance box in such a way that the portions of the box with higher yield lies in the feasible region. The yield is directly estimated using the joint cumulative distribution function (CDF) over the tolerance box requiring no numerical integration and saving considerable computational complexity for multidimensional problems. For this reason, any arbitrary distribution can be considered for random parameters and the problem is not restricted to normality assumptions. Numerical examples, verified by Monte-Carlo simulations, demonstrate that optimal designs significantly increase the yield. The advantage of the proposed design optimization method is that the yield can be maximized in early design stages without tightening tolerances or increasing the fabrication cost and complexity. The application of the presented method is not limited to tunable capacitors and can be extended to other MEMS devices.     

Accurate Conjunction of Yield Models for Fault-Tolerant Memory Integrated Circuits

Critical defects, i.e., faults, inevitably occur during semiconductor fabrication, and they significantly reduce both manufacturing yield and product reliability. To decrease the effects of the defects, several fault-tolerance methods, such as the redundancy technique and the error correcting code (ECC), have been successfully applied to memory integrated circuits. In the semiconductor business, accurate estimation of yield and reliability is very important for determining the chip architecture as well as the production plan. However, a simple conjunction of previous fault-tolerant yield models tends to underestimate the manufacturing yield if several fault-tolerance techniques are employed simultaneously. This paper concentrates on developing and verifying an accurate yield model which can be applied successfully in such situations. The proposed conjunction model has been derived from the probability of remaining redundancies and the average number of defects after repairing the defects with the remaining redundancies. The validity of the conjunction yield model is verified by a Monte Carlo simulation.      

Reliability versus yield and die location in advanced VLSI

The results of multiple correlations between reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures.The model that reliability defect density is proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.     

Burn-in effect on yield

By removing infant mortalities, burn-in of semiconductor devices improves reliability. However, burn-in may affect the yield of semiconductor devices since defects grow during burn-in and some of them end up with yield loss. The amount of yield loss depends upon burn-in environments. Another burn-in effect is the yield gain. Since yield is a function of defect density, if some defects are detected and removed during burn-in, the yield of the post-burn-in process can be expected to increase. The amount of yield gain depends upon the number of defects removed during burn-in. In this paper we present yield loss and gain expressions and relate them with the reliability projection of semiconductor devices in order to determine burn-in time     

Acceptable Testing of VLSI Components Which Contain Error Correctors

If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes maybe employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thns obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.     

Reliability assessment of the metallized film capacitors from degradation data

Metallized film pulse capacitors are the key component of an inertial confinement fusion (ICF) facility. The reliability of the capacitors has a significant impact on the operational reliability and maintenance expenses of the entire system. For high-reliability capacitors that do not normally fail in a reasonable length of time, it is difficult to assess reliability by using the traditional time-to-failure analysis method. Analyzing the degradation mechanisms of the metallized film capacitors, this paper presents a life distribution model whose parameters can be estimated from the degradation measures of the capacitors, and which has proven to be very accurate and economical in test costs.     

Using statistically designed experiments to improve reliability andto achieve robust reliability

This tutorial explains statistically designed experiments which provide a proactive means to improve reliability as advocated by Genichi Taguchi. That is, by systematic experimentation, the important parameters (factors) affecting reliability can be identified along with parameter values that yield reliability gains. In addition to improving reliability, Taguchi's robust design can be used to achieve robust reliability; that is, to make a process or product reliability insensitive to factors which are hard or impossible to control. Robust design is also implemented using statistically designed experiments. This paper presents classes of experimental plans for reliability improvement and robust reliability. An important feature of the reliability data collected from such experiments is censoring which occurs when some of the experimental units have not failed by the end of the experiment. Consequently, the analysis methodology must account for these censored data which are likely to occur in light of the ever increasing reliability of today's products. Several appropriate methods are discussed briefly. These experimental plans and analysis methods are illustrated using three documented experiments which improved fluorescent lamp and industrial thermostat reliability and which achieved robust reliability for night-vision goggles     

Reliability Techniques in the Service of Industry

Failures which occur in any industrial activity reduce the profitability and safety of commercial ventures. Numerical estimates of reliability, availability, and profitability are based on an understanding of the fundamental concepts of reliability engineering. These estimates assist comparison of alternative design or improvement strategies for process plant. Although a reliability assessment is concerned largely with equipment failures, the important part played by human reliability can be estimated and included in such studies. Plant reliability interacts with the morale of the workforce; morale is unfortunately not easy to quantify. The methods and procedure of a reliability analysis are described. A degree of flexibility in the assessor's approach is useful when the rigour of the study must be adjusted to suit practical cost considerations.