Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Ultrathin gate oxide grown on nitrogen-implanted silicon for deepsubmicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0×10¹⁴/cm² and 2.0×10¹⁴ /cm². Initial O₂ injection method was applied for gate oxidation. The method is composed of an O₂ injection/N₂ anneal/main oxidation, and the control process is composed of a N₂ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 μm have been fabricated by use of the method. Compared to the control process, the initial O₂ injection process increases the amount of nitrogen piled up at the Si/SiO₂ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved     

Reduction of RIE-damage by N2O-anneal of thermal gateoxide

We have investigated RIE-induced damage in MOS devices with thermal oxide as well as N₂O-annealed oxide as gate dielectrics. A systematic improvement in robustness against RIE-induced damage is seen when N₂O flow rate and/or N₂O anneal temperature are increased. We have demonstrated a N₂O anneal process at 900°C, which provides a robust SiO₂/Si interface against plasma damage and hot carrier stress     

Suppression of the boron penetration induced Si/SiO2interface degradation by using a stacked-amorphous-silicon film as thegate structure for pMOSFET

The authors report that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO₂ interface. An atomically flat Si/SiO₂ interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p⁺ poly-Si gate MOS devices even with the annealing temperature as high as 1000°C     

Avalanche electron injection in 4-nmSi3N4/8-nm SiO2 dielectric structure:turn-around phenomenon and Si-SiO2 interface degradation

Charge trapping and interface-state generation in very thin nitride/oxide (4-nm Si₃N₄+8-nm SiO₂) composite gate insulators are studied as a function of gate electrode work function and bottom oxide thickness. The behavior of the trapped positive charge under bias-temperature stress after avalanche electron injection (AEI) is investigated. Evidence is presented that secondary hole injection from the anode (gate/Si₃N₄ interface) and subsequent trapping near the SiO₂-Si interface result in a turnaround of the flatband voltage shift during AEI from the substrate. Just like the thermal oxides on Si, slow-state generation near the SiO₂-Si interface and boron acceptor passivation in the surface-space charge layer of the Si substrate are also observed after AEI in these nitride/oxide capacitors, and they are found to be strongly related to the secondary hole injection and trapping. Finally, interface-state generation can take place with little secondary anode hole injection and is enhanced by the occurrence of hole trapping     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

Temperature-dependent Sellmeier coefficients and chromaticdispersions for some optical fiber glasses

Temperature-dependent Sellmeier coefficients are necessary to optimize optical design parameters of the optical fiber transmission system. These coefficients are calculated for fused silica (SiO₂ ), aluminosilicate, and Vycor glasses for the first time to find the temperature dependence of chromatic dispersion at any wavelength from UV to 1.7 μm. The zero dispersion wavelength λ₀ (1.273 μm for SiO₂, 1.393 μm for aluminosilicate, and 1.265 μm for Vycor glasses at 26°C) varies linearly with temperature, and dλ₀/dT is 0.03 nm/K for aluminosilicate and Vycor glasses, whereas for SiO₂ it is 0.025 nm/K. This study interprets the recently observed experimental value of dλ₀/dT for two dispersion shifted optical fibers; and the dominantly material origin of dλ₀/dT is confirmed here as a fundamental property of the optical fiber glasses     

A study of interface trap generation by Fowler-Nordheim andsubstrate-hot-carrier stresses for 4-nm thick gate oxides

The generation of interface traps by different stresses to 4-nm thick SiO₂ gate oxide is studied. Four different kinds of constant current stresses were applied. The interface-trap density (D _it) generation due to hot holes under V_G<0 Fowler-Nordheim (FN) stress was characterized using quantum-yield measurement and substrate-hot-hole (SHH) stress. The interface-trap density (D_it) generated by SHH stress increases as gate-oxide field increases. Substrate-hot-electron (SHE) stress generates much less interface-trap density (D_it) than SHH stress. It is also observed that N₂O-grown gate-oxide has smaller hole-injection probability but larger electron-injection probability than O₂-grown oxide. N₂O-grown gate oxide is shown to have less SHH stress-induced interface traps than O₂-grown oxide in p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) devices     

Temperature and optical characteristics of tin oxide membrane gateISFET

The influence of temperature and optical effects on ISFET performance are important. In this study, the temperature characteristics of the SnO₂/Si₃N₄/SiO ₂/Si ISFET are investigated by the zero temperature coefficient (T.C.) adjustment and the dual FET's configuration, respectively. The result show that a zero T.C. of the SnO₂ gate ISFET can be achieved when the appropriate operation current was set. Subsequently, the T.C. of tin oxide membrane/electrolyte interface can be evaluated by the dual FETs configuration. On the other hand, due to the SnO₂ gate ISFET is sensitive to the light exposure, thus in order to improve this drawback, a multi-structure ISFETs: SnO ₂/Al/SiO₂/Si₃N₄/Si ISFETs have been developed. In this structure, aluminum is used as a light shield, and the tin oxide is used as a pH sensitive layer. The results show the ISFETs with aluminum as a light shield have low light sensitivity compared with ISFETs without aluminum as a light shield     

A Comparative Study of HfTaON/SiO2 and HfON/SiO2 Gate Stacks With TaN Metal Gate for Advanced CMOS Applications

The electrical characteristics of a novel HfTaON/SiO₂ gate stack, which consists of a HfTaON film with a dielectric constant of 23 and a 10-Aring SiO₂ interfacial layer, have been investigated for advanced CMOS applications. The HfTaON/SiO₂ gate stack provided much lower gate leakage current against SiO₂ , good interface properties, excellent transistor characteristics, and superior carrier mobility. Compared to HfON/SiO₂, improved thermal stability was also observed in the HfTaON/SiO₂ gate stack. Moreover, charge-trapping-induced threshold voltage V _th instability was examined for the HfTaON/SiO₂ and HfON/SiO₂ gate stacks. The HfTaON/SiO₂ gate stack exhibited significant suppression of the V_th instability compared to the HfON/SiO₂, in particular, for nMOSFETs. The excellent performances observed in the HfTaON/SiO₂ gate stack indicate that it has the potential to replace conventional SiO₂ or SiON as gate dielectric for advanced CMOS applications     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Effect of physical stress on the degradation of thinSiO2 films under electrical stress

In this work, we demonstrate that for ultrathin MOS gate oxides, the reliability is closely related to the SiO₂/Si interfacial physical stress for constant current gate injection (V_g^- ) in the Fowler-Nordheim tunneling regime. A physical stress-enhanced bond-breaking model is proposed to explain this. The oxide breakdown mechanism is very closely related to the Si-Si bond formation from the breakage of Si-O-Si bond, and that is influenced by the physical stress in the film. The interfacial stress is generated due to the volume expansion from Si to SiO₂ during the thermal oxidation, and it is a strong function of growth conditions, such as temperature, growth rate, and growth ambient. Higher temperatures, lower oxidation rates, and higher steam concentrations allow faster stress relaxation through viscous flow. Reduced disorder at the interface results in better reliability. Fourier transform infrared spectroscopy (FTIR) technique has been used to characterize stress in thin oxide films grown by both furnace and rapid thermal process (RTP). In conjunction with the Gibbs free energy theory, this model successfully predicts the trends of time-to-breakdown (t_bd) as a function of oxide thickness and growth conditions. The trends of predicted t_bd values agree well with the experimental data from the electrical measurement     

High performance sub-0.25 μm devices using ultrathinoxide-nitride-oxide gate dielectric formed with low pressure oxidationand chemical vapor deposition

An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 μm device with high performance was fabricated for which the gate dielectric reliability was studied using both Fowler-Nordheim tunneling stress and hot carrier aging. The results from both techniques demonstrate that the device lifetime is longer than 100 years. Auger spectroscopy shows that there is about 9 at.% nitrogen at the SiO₂/Si interface. However, no transconductance degradation is observed     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

High-quality oxide/nitride/oxide gate insulator for GaN MISstructures

We report on a SiO₂/Si₃N₄/SiO₂ (ONO) gate insulator stack deposited on GaN by jet vapor deposition (JVD) technique. Capacitors fabricated using the JVD-ONO on GaN are characterized from room temperature to 450°C using capacitance-voltage (C-V), current-voltage (I-V), AC conductance, and constant-current stress measurements. We find excellent operating characteristics over the measured range, most notably: (1) very low leakage current, (2) extremely high hard-breakdown strength, (3) low interface-trap density, and (4) low net dielectric-charge density. Moreover these performance figures remain well within acceptable limits even for operating temperatures as high as 150°C. In addition, we measure both the capture cross-section of the interface traps and the surface-potential fluctuation at the GaN/ONO interface. All results suggest that JVD-ONO is an excellent choice for a gate dielectric in GaN-based MISFETs     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S