直接键合硅片界面键合能的理论分析

直接键合硅片界面的键合能依赖于界面成键的密度,是退火温度和时间的函数,界面反应激活能决定着成键的行为．硅片键合能随退火温度分两步增加,这种现象被归因于界面反应存在两种不同的激活能．将硅本征氧化层与硅热氧化层两种键合界面在退火过程中的行为进行了理论分析与比较．硅本征氧化层的键合能随温度的增加要比热氧化层界面的大．键合能的饱和时间与激活能密切相关．     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

硅键合的实现及键合质量检测

通过大量实验并对硅高温键合的机理进行研究发现,键合高温处理温度和时间是实现良好键合的关键。通过对键合处理温度和时间的优化,已成功地实现了直径为1.5英寸硅片的大面积、均匀键合,键合体抗拉强度达100kg/cm~2,中间氧化层厚度在自然氧化层与2μm之间。通过预刻键合界面测试图形和分割解剖键合片,证实了红外热像技术检测键合界面空洞的可靠性,对键合不良区域的分辨率为2×2mm~2。     

硅片直接键合机理及快速热键合工艺

本文的理论与实验结果说明,硅片表面吸附的OH团是室温下硅片相互吸引的主要根源。采用SIMS和红外透射谱定量测量了OH吸附量。开发了表面活化技术。发现键合强度随温度而增大是键合面积增加所致。SiO_2/SiO_2键合之界面中各种物质的扩散及氧化层粘滞流动可以消除界面微观间隙。经表面活化的两硅片经室温贴合,150℃预键合,800℃,2小时退火后经1200℃,2分钟快速热键合可实现完善的键合且原有杂质分布改变很小,为减薄工艺提供了一个技术基础。     

样品键合:键合工艺的研究与检查

硅片直接键合是一种为传感器工艺提供广泛应用范围的新技术.它仅需基本的标准硅加工设备,它的基本工艺是把两个氧化的样片在室温下键合,然后高温退火,可得到隐埋氧化层.加上掺杂和薄的外延淀积可以得到多种腐蚀自停止层.结合各向异性及优向腐蚀技术,则使膜片生产、在硅氢化中冷却沟道的生产和微机械器件的生产等各种各样的应用更加灵活.     

硅／硅键合界面的正电子湮没分析

硅/硅键合是硅功率器件,功率集成电路以及集成传感器衬底制备新技术之一。键合界面的缺陷直接影响器件性能。我们采用正电子湮没技术对N/N~+硅键合片界面缺陷进行了研究。由正电子湮没谱可知:键合引入了界面缺陷,但其缺陷密度小于热扩散形成的N~-/N~+片而引入的缺陷。界面缺陷主要是一些复杂的空位团和微型空洞组成。而且在不同的退火温度下,缺陷状态不同,在高于键合温度下退火。可使键合片具有与原始硅片相近的特性。     

硅片直接键合的微观动力学研究

基于直接键合硅片表面能与退火温度的关系曲线,定量讨论了键合时键合界面上的微观动力学变化过程。首次提出五阶段键合模型计算值与实测表面能曲线相一致,初步确定了键合过程中界面发生的微观反应机理。     

采用界面薄层氧化硅的硅片直接键合技术研究

本文研究了采用界面薄层氧化硅的硅片直接键合技术。利用原子力显微镜（AFM）和剪切力测试分别表征表面粗糙度和键合强度随着薄层氧化硅厚度的变化情况。对比了采用热氧化和等离子体增强化学气相沉积法（PECVD）两种方法对晶片粗糙度及键合强度的影响。结果表明采用热氧化和PECVD沉积薄层氧化硅做硅片直接键合,键合强度分别可以达到18MPa和8MPa,键合强度随着薄层界面氧化硅厚度的增加而下降,这对于MEMS器件制备及其他硅片直接键合的应用都具有十分重要的指导意义。     

硅片直接键合界面的存在对器件性能的影响

利用电子透射显微镜(TEM)和俄歇分析仪(AES)观察硅片直接键合界面结构,在界面存在一个小于2nm厚的非晶区-硅氧化物。此界面具有良好的吸杂效应,在同一退火温度下,退火时间愈长,吸杂现象愈明显。因此键合界面的存在改善了晶体管的性能。     

压阻加速度计的Au-Si共晶键合

通过将压阻加速度计上帽与结构片的键合(365℃保温10min),再进行下帽与结构片的键合(380±10℃保温20min),成功进行了三层键合.测得的键合强度约为230MPa.硅片-基体/SiO2/Cr/Au层和硅片之间键合时,SiO2溶解而形成CrSi2硅化物.共晶反应因Cr层而被推迟,键合温度高出共晶温度20℃左右,从而避免了由于Au元素向硅中扩入而造成的污染,进而避免可能造成的对集成微电子器件性能的影响.试验还证明硅基体-SiO2/Cr/Au/Poly-Si/Au键合层结构设计模型也遵循这一键合过程中的原子扩散理论.     

Si/Si直接键合界面性质的研究

通过三步直接键合方法实现了 Si/ Si键合。采用 XPS、FTIR、I-V、拉伸强度等手段对 Si/ Si键合结构的界面特性作了深入广泛的研究。研究结果表明 ,高温退火后 ,在键合界面没有 Si-H和 Si-OH网络存在 ,键合界面主要由单质 Si和不定形氧化硅 Si Ox 组成。同时 ,研究还表明 ,I-V特性和键合强度强烈地依赖于退火温度。     

晶圆键合技术在LED应用中的研究进展

简要介绍了晶圆键合技术在发光二极管(LED)应用中的研究背景,分别论述了常用的黏合剂键合技术、金属键合技术和直接键合技术在高亮度垂直LED制备中的研究现状,包括它们的材料组成和作用、工艺步骤和参数以及优缺点.其中,黏合剂键合是一种低温键合技术,且易于应用、成本低、引入应力小,但可靠性较差;金属键合技术能提供高热导、高电导的稳定键合界面,与后续工艺兼容性好,但键合温度高,引入应力大,易造成晶圆损伤;表面活化直接键合技术能实现室温键合,降低由于不同材料间热失配带来的负面影响,但键合良率有待提高.     

Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed     

Si-Si直接键合的杂质分布

在Si-Si直接键合过程中,界面处存在一层很薄的厚度恒定的本征SiO2.Si对SiO2中的杂质的抽取效应,导致了杂质在界面处的浓度大大降低,根据改进了的杂质在Si-Si直接键合片中分布模型,推导出了杂质分布的表达式,在理论上和实验上都对该式进行了验证.杂质通过SiO2再向Si中扩散的杂质总量与Si-Si扩散相比大大减少,使所形成的p-n 结的结深减小.     

Some observations on charge buildup and release in silicon dioxide irradiated with low energy electrons

The positive charge buildup produced in silicon dioxide by low energy electrons (0 to 30 keV) has been investigated as a function of beam energy and oxide thickness. The induced charge, as evidenced by displacement of capacitance versus voltage plots, was found to be a function of the beam energy dissipated within the oxide in the vicinity of the oxide-silicon interface. The charge induced at a particular fluence level in an oxide of given thickness increases with energy up to some level Emaxbeyond which the charge buildup rate falls off as the energy is increased further. Continued falloff in the buildup rate was observed in several samples irradiated at energies of 200 keV and 1 MeV. Emaxhas been found to correspond to the beam energy which, according to predicted range-energy data, produces maximum energy dissipation per unit path length in the oxide near the silicon interface. Constant temperature annealing of irradiated MOS samples has indicated that the annealed charge is linearly dependent on the logarithm of elapsed time over a finite time interval. This is particularly evident at room temperature where a linear dependence on In (t) has been observed out to 10⁵seconds. Such a time dependence of released charge can result either from thermal activation of trapped carriers from a uniform trap distribution or from thermal emission of recombination electrons over a Schottky barrier from the silicon into the oxide; however, both of these models predict the released charge to be a linear function of absolute temperature. A much stronger temperature dependence has been observed during these experiments.     

Annealing characteristics of hot carrier induced damage in n-channel MOSFETs

The recovery process of hot carrier induced degraded device parameters in n-channel MOSFETs has been analysed by both isothermal and isochronal annealing. A wide distribution of activation energies of hot carrier induced damage, with a peak at around 0·9eV is observed. It can be seen that isochronal annealing has advantages over isothermal annealing in recovering the degraded device characteristics in comparatively less time. Bias annealing of the device reveals that initially the annealing of trapped oxide charges increases the interface state density, after reaching the peak value interface states anneal as a logarithmic function of time. The energy distribution of hot carrier induced interface states is similar to radiation induced interface states after a few hours of annealing at room temperature.     

Mechanism of Wafer Bonding Process

The basic force and bonding energy in wafer bonding have been revealed in this study.The basic cause for bonding contributes to the interatomic attractive forces between surfaces or the rduction of surface energies.The amplitude of roughness component can not exceed the criterion if wafer pair is bondable.The bonding behavior and challenge during annealing have been investigated.